Do you Know about Small Scale Core companies & Vacancies

Small Scale Companies in Chennai

Companies are broadly categorized as

• Start up
• small scale,
• medium scale, 
• Large scale & 
• Very large scale or MNC companies

Most of the MNC , large scale and medium scale companies place advertisements and approach job portals such as Naukri,Monster etc to recruit candidates. They also take regular basis and a complete HR team will be there to work for it.They also give advertisements in various media sources or they purchase the candidates data base in bulk and conduct frequent walk ins.

When freshers in search of job browse google page most of the top job portal site will come to their view and they easily register their resumes in the job portals and start searching the job by using key words.

Some of the job seekers approach consultancies back door, front bla bla etc Few of the job seekers approach the companies directly by sending direct mail to their mailbox.Very rare peoples its a old technique too .. go directly into the Companies and give their resumes.

So many strategies they follow to find appropriate job. My point is... Job seekers are following these methods can reach only the 3 catagory of companies such as MNC, Large & Medium scale.They cannot reach the remaining two catagory  of companies.

Companies such as Start up company - where the employee size will be less than 5 and Small scale companies - where the number of employees size will be more than 10 and less than 25 the maximum.we call these two type of companies in general as SSI Small scale industries.

These companies cannot place their ads in top job portals. they simply approach the govt training centres, skill development centres , private training centres to get required candidates. they do participate in job mela and recruit candidates.

SSI companies also have less number of  recruitment cycle. they simply look for skill sets not your backlogs too... develop the unique skill set, do work on it consistently.. more info on ssi companies will be posted soon.

keep learning...!!!


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Design of Low power Built in self calibration and Digital Trim technique project Basepaper explanation

 VLSI Project for ME / BE / BTECH

Advantages :

• Configurable Design architecture enable the system parameter variable
• Digital Trim technique can be useful for self tolerant of errors
• Code re-usability and Behavioral architecture

 Software Required

• MODELSIM / QUARTUS ||
• MICROWIND
• XILINX ISE

 

Contact us for Source Code : 8939504005

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Phd projects in chennai: VLSI Software Course Modules

ADVANCED TRAINING IN VLSI DESIGN & FPGA IMPLEMENTATION

Course Modules

Module1 :VLSI Technology & industrial applications
Module2: VLSI - CMOS Design methodology
Module3: VLSI System architecture 
Module4:Digital electronics advanced
Module5:Creating Digital Logics - advanced
Module6: VHDL Programming
Module7:EDA Tools Design methodology
Module8:FPGA Hardware Design
Module9: Testing & Validation
Module10: Equipments & Devices
Module11: Quantum Physics & Nano Tech
Module12:VLSI Artificial Intelligence
Module13:PROJECT
     
100% JOB ASSURED


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An Efficient VLSI Architecture for Data Encryption Standard and its FPGA Implementation

An Efficient VLSI Architecture for Data Encryption Standard and its FPGA Implementation

ABSTRACT

Design of cryptography based applications, including health-monitoring and biometric data based recognition system, need short-term data security. Data encryption standard (DES) is well-suited for the implementation of low-cost lightweight cryptography applications. In this paper, we studied an efficient VLSI architecture for DES algorithm based encryption/decryption engine. Depending upon the encryption/decryption needs, the same set of architecture performs both encryption and decryption operations. In the implementation of DES algorithm, a chain of multiplexer-based architecture is used to implement the substitution operations (SBoxes). The existing architecture is modeled in the VHDL design language and synthesized in the Xilinx field-programmable gate array (FPGA) device. Hardware synthesis result shows that the proposed design utilizes only 1.07 % slice LUTs, 0.31 % slice registers and 29.22 % of bonded IOBs of the FPGA device fabric.

EXISTING DESIGN

In the existing system, an efficient VLSI architecture for DES algorithm based encryption/decryption engine. Depending upon the encryption/decryption needs, the same set of architecture performs both encryption and decryption operations. In the implementation of DES algorithm, a chain of multiplexer-based architecture is used to implement the substitution operations (SBoxes). The existing architecture is modeled in the VHDL design language and synthesized in the Xilinx field-programmable gate array (FPGA) device. Hardware synthesis result shows that the proposed design utilizes only 1.07 % slice LUTs, 0.31 % slice registers and 29.22 % of bonded IOBs of the FPGA device fabric.


PROPOSED DESIGN
In the proposed Design, a high speed variable Pseudorandom key is being generated. Encryption and decryption can also be implemented in high speed of operation up to 1 GHZ. It is also planned to design both the encryption and decryption in a mutual understanding manner so that the decryption always depends upon the operations and logics held in encrypted module. This mode of operation assures even more accuracy and secure data transfer.Implementation can be done in XILINX ISE, XC9572XL Low power CoolRunner kit can be used for hardware implementation. Power consumption area can be calculated as well.


Advantages of Proposed System

· Secure Communication since

· Logical dependence on encryption and Decryption

· Variable key Frequency

Software Required
Simulation : MODELSIM 6.3 G ALTERA
Implementation : XILINX ISE 10.5
Language : VHDL
Power : XILINX XPE


· User configurable Key also given


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Design and implementation of fault tolerant and fault correcting Spintronic Flip flop

Design and implementation of fault tolerant and fault correcting Spintronic Flip flop

Overview of Existing System

With technology down scaling, static power has become one of the biggest challenges in a system on chip. Normally off computing using nonvolatile (NV) sequential elements is a promising solution to address this challenge. Recently, many NV shadow flip-flop architectures have been introduced in which magnetic tunnel junction (MTJ) cells are employed as backup storing elements. Due to the emerging fabrication processes of magnetic layers, MTJs are more susceptible to manufacturing defects than their CMOS counterparts. Moreover, unlike memory arrays that can effectively be repaired with well-established memory repair and coding schemes, flip-flops scattered in the layout are more difficult to repair. Therefore, without effective defect and fault tolerance for NV flip-flops, the manufacturing yield will be affected severely. In this paper a fault-tolerant NV latch (FTNV-L) design, in which several MTJ cells are arranged in such a way that it is resilient to various MTJ faults. The simulation results show that our proposed FTNV-L can effectively tolerate all single MTJ faults with a considerably lower overhead than traditional approaches.

Proposed System

Design of fault tolerant and fault correcting Spintronic Flip flop is implemented here with active dynamic fault correcting scheme. The design implies in such a way that it can able to detect as well as correct the errors occur due to junction tunneling. The internal resistance and capacitance even though plays a protective block for leakage of current and voltages, the junction leakages are happens beyond that. The leakage of current produces power dissipation in the form of heat. The architecture is designed in such a way it will avoid slow leakage faults.

Software required

Language                                       :        VHDL

Simulation Tool : MODELSIM 6.3G,QUARTUS || ,XILINX ISE, MICROWIND

 


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VHDL CODE FOR GATES

VHDL CODE FOR GATES

To become a VLSI designer you should be strong in Digital electronics so keep on learning digital logic and ideas.  Normally in digital electronics two broad catagories of logics we can tell, Combinational circuits and Sequential circuits.

Combinational Logics or Circuits
Combinational logics are logics in which the outputs depends upon present inputs only
examples of combinational circuits are Gates, adders,subtractors,multiplexers,de-multiplexers etc

Sequential Circuits
Sequential Circuits are logics in which the output depends upon present as well as past outputs
examples of sequential circuits are Flipflops , latches, counters etc

Let us start learning from Combinational circuits from Here

Here i give you a Sample VHDL code for combinational Gates

VHDL Code for Logical gates

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

entity gate is
port(a,b: in std_logic;
y1,y2,y3,y4,y5,y6,y7: out std_logic);
end entity gate;

architecture behave of gate is
begin
-- AND GATE
 y1 <= a and b;
--OR GATE
 y2 <= a or b;
--NOT GATE
 y3 <= not a;
--XOR GATE
 y4 <= a xor b;
--XNOR GATE
y5 <= a xnor b;
end behave;

Simple Tools  used for Verifying the Code

MODELSIM 6.3G ALTERA version tool is useful for simply running the code
else you can use XILINX ISE for simulating the code

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Top 20 VLSI Project titles for the year 2017-18

 Top 20 VLSI Project titles for the year 2017-18

1.          A Fully Integrated Discrete-Time Super heterodyne Receiver

2.          An FPGA-Based Hardware Accelerator for Traffic Sign Detection

3.          Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit

4.          STT-RAM Buffer Design for Precision-Tunable General-Purpose Neural Network Accelerator

5.          Deep Convolutional Neural Network Architecture With Reconfigurable Computation Patterns

6.          A 65-nm CMOS Constant Current Source With Reduced PVT Variation

7.          Design of Power and Area Efficient Approximate Multipliers

8.          A High-Efficiency 6.78-MHz Full Active Rectifier With Adaptive Time Delay Control for Wireless Power Transmission

9.          A 100-mA, 99.11% Current Efficiency, 2-mVpp Ripple Digitally Controlled LDO With Active Ripple Suppression

10.      VLSI Extreme Learning Machine: A Design Space Exploration DRAM-Based Intrinsic Physically Unclonable Functions for System-Level Security and Authentication

11.      RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing

12.      A 110-nm CMOS 0.7-V Input Transient-Enhanced Digital Low-Dropout Regulator With 99.98% Current Efficiency at 80-mA Load

13.      A High-Speed and Power-Efficient Voltage Level Shifter for Dual-Supply Applications

14.      A 6-mW, 70.1-dB SNDR, and 20-MHz BW Continuous-Time Sigma-Delta Modulator Using Low-Noise High-Linearity Feedback DAC 

15.      10T SRAM Using Half- VDD Precharge and Row-Wise Dynamically Powered Read Port for Low Switching Power and Ultralow RBL Leakage

16.      A Smaller, Faster, and More Energy-Efficient Complementary STT-MRAM Cell Uses Three Transistors and a Ground Grid: More Is Actually Less

17.      Dual-Quality 4:2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers

18.      High-Current Drivability Fibonacci Charge Pump With Connect-Point-Shift Enhancement

19.      High-Throughput and Energy-Efficient Belief Propagation Polar Code Decoder 

20.      Silicon Demonstration of Hardware Trojan Design and Detection in Wireless Cryptographic ICs

 



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How to write a VHDL architecture

VHDL Architecture

The structure of VHDL Programming consists of entity and architecture

As explained already , entity is used to define input and output port informations

Architecture tells you the functional behaviour of the Logic which we are writing

One entity can address multiple architecture, whereas multiple entities cannot able to address one architecture, the design structure is not possible

 

SYNTAX

ARCHITECTURE <NAME> OF <ENTITY_NAME> IS

BEGIN

SEQUENTIAL & COMBINATIONAL LOGIC DECLARATIONS

END <NAME>;

VHDL EXAMPLE

architecture for Half adder:

***********************************************************

architecture half_adder of ha is

begin

sum <= a XOR b;

carry <= a AND b;

end half_adder;

***********************************************************

How to write VHDL entity

VHDL ENTITY

The vhdl code starts with the entity declaration and architecture declaration

Entity is nothing but the black box of the digital module going to be designed

It tells us the input ports and output ports configurations

It also contains the info about external connections to the other modules

There are input ports which is refered as IN , output ports which is referred as OUT and inbetween INOUT port also there where the signal act as input as well as output

Entity starts with a key word ENTITY, label can be any user defined name

A simple VHDL Example how to write entity is shown below


SYNTAX

ENTITY <ENTITY NAME> IS
       PORT(input output declarations.......)
END ENTITY<ENTITY NAME>;

 Example


ENTITY and_gate IS
       PORT(a,b : IN STD_LOGIC;
                    c   :OUT STD_LOGIC);
END ENTITY<ENTITY NAME>;

Hope it is Useful !!
Keep Reading

 *****************************************************************************
 

How to write VHDL Library ?

VLSI Projects in chennai

VHDL Library :

The following are the list of commonly used library files in VHDL language, Depends upon the algorithm requirement these library can be modified.

        library IEEE;
        use IEEE.std_logic_1164.all;
        use IEEE.std_logic_textio.all;
        use IEEE.std_logic_arith.all;
        use IEEE.numeric_bit.all;
        use IEEE.numeric_std.all;
        use IEEE.std_logic_signed.all;
        use IEEE.std_logic_unsigned.all;
        use IEEE.math_real.all;
        use IEEE.math_complex.all;

Some of the libraries may be third party library or user defined library. if the code consists of 

complex multiplications which used in FFT, DFT etc then the user should add use IEEE.math_complex.all Library

VHDL EXAMPLE

**************************************************************************************************

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_TEXTIO.ALL;

**************************************************************************************************

try yourself these codes. More coding techniques will be updated in our next post.

Happy Learning!!