VLDL code for predictive tuning circuit

Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.math_real.all;
use ieee.numeric_std.all;


ENTITY Predictive_control_single is
port(clk,clr: in std_logic;
pred_in : in real;
adc_resol: out real);
end Predictive_control_single;


architecture behave of Predictive_control_single is

signal sel : std_logic_vector(3 downto 0);


begin
   
mem_predictor:process(pred_in,clk,clr)
begin
if clr='1' then
    sel<="0000";
    elsif rising_edge(clk) then
       
       if (pred_in>0.00) and (pred_in<100.00) then 
             sel<="0001";
       end if;

if (pred_in>100.00) and (pred_in<125.00) then 
             sel<="0001";
       end if;

if (pred_in>125.00) and (pred_in<150.00) then 
             sel<="0010";
       end if;

if (pred_in>150.00) and (pred_in<175.00) then 
             sel<="0011";
       end if;

if (pred_in>175.00) and (pred_in<200.00) then 
             sel<="0100";
       end if;

if (pred_in>200.00) and (pred_in<225.00) then 
             sel<="0101";
       end if;

if (pred_in>225.00) and (pred_in<350.00) then 
             sel<="0110";
       end if;

if (pred_in>350.00) and (pred_in<475.00) then 
             sel<="0111";
       end if;

if (pred_in>475.00) and (pred_in<500.00) then 
             sel<="1000";
       end if;

if (pred_in>500.00) and (pred_in<725.00) then 
             sel<="1001";
       end if;

   if (pred_in>725.00) and (pred_in<850.00) then 
             sel<="1010";
       end if;   

if (pred_in>850.00) and (pred_in<975.00) then 
             sel<="1011";
       end if;

if (pred_in>975.00) and (pred_in<1200.00) then 
             sel<="1100";
       end if;
             
end if;       
end process mem_predictor;   
   

sel_range:process(sel)
begin
    if clr='1' then

adc_resol<= 0.000;
        else
        case sel is
            when "0001" => adc_resol <=0.500;

           
            when "0010" => adc_resol <=1.000;

                           
            when "0011" => adc_resol <= 1.500;


            when "0100" => adc_resol <= 2.000;

                          
            when "0101" => adc_resol <= 2.500;

                          
            when "0110" => adc_resol <= 3.000;

                          
            when "0111" => adc_resol <= 3.500;

                           
            when "1000" => adc_resol <= 4.000;

                           
            when "1001" => adc_resol <= 4.500;

                           
            when "1010" => adc_resol <= 5.000;


            when "1011" => adc_resol <= 5.500;

                           
            when "1100" => adc_resol <= 6.000;

          
              when others => adc_resol <= 0.000;

              end case;
          end if;         
                                                                  
end process sel_range;


 

end behave;   

vlsi implementation of FFT

Configurable FFT using mixed radix form

Module 1: Design of FFT Block

The FFT computation is accomplished in three stages. The x(0) until x(15) variables are denoted as the input values for FFT computation and X(0) until X(15) are denoted as the outputs. The pipeline architecture of the 16 point FFT is shown in Fig 4.1 consisting of butterfly schemes in it. There are two operations to complete the computation in each stage. Which is implemented in the FFT BLOCK.

Module 2: Design of Control unit

FFT Computation can be controlled using a software controlled finite state machine control algorithm written in VHDL.Reference signals are used to control the data flow and address flow.

Module 3: Design of adder & Subtractor section

This module consists of adder and subtractor sections used for calculating the fft co-efficients. Here in our project we have a single adder and using timing control the number of adder can be reduced.

Module 4: Design of Integration module

This module consists of integration of sub modules with respect to clock and other synchronization procedures are done over here.