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VHDL CODE FOR DIGITALLY CONTROLLED OSCILLATOR
Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity dco is
port(clk,clr:in std_logic; cy: in std_logic;
dcoout: out std_logic);
end dco;
architecture behave of dco is
signal q,qa: std_logic;
signal dcoout_1,dcoout_2,tempdcoout : std_logic;
begin
tff_dco: process(clk,clr)
begin
if clr='1' then
q<='0';
elsif rising_edge(clk) then
q <= not q;
end if;
end process tff_dco;
tff_dco_a: process(q,clr)
begin
if clr='1' then
qa<='0';
elsif rising_edge(q) then
qa <= not qa;
end if;
end process tff_dco_a;
dcoout_1 <= ( not cy ) and q;
dcoout_2 <= ( cy ) and qa;
tempdcoout <= dcoout_1 or (dcoout_2) after 10 ps;
dcoout <= tempdcoout and clk;
end behave;
VHDL CODE FOR VARIOUS REFERENCE SIGNAL GENERATOR
Get utilize some of my Basic VLSI Codes !!1 Contact me for any kind of Doubts.
Good Luck !!
VHDL CODE FOR DIGITALLY CONTROLLED OSCILLATOR
Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity dco is
port(clk,clr:in std_logic; cy: in std_logic;
dcoout: out std_logic);
end dco;
architecture behave of dco is
signal q,qa: std_logic;
signal dcoout_1,dcoout_2,tempdcoout : std_logic;
begin
tff_dco: process(clk,clr)
begin
if clr='1' then
q<='0';
elsif rising_edge(clk) then
q <= not q;
end if;
end process tff_dco;
tff_dco_a: process(q,clr)
begin
if clr='1' then
qa<='0';
elsif rising_edge(q) then
qa <= not qa;
end if;
end process tff_dco_a;
dcoout_1 <= ( not cy ) and q;
dcoout_2 <= ( cy ) and qa;
tempdcoout <= dcoout_1 or (dcoout_2) after 10 ps;
dcoout <= tempdcoout and clk;
end behave;
VHDL CODE FOR VARIOUS REFERENCE SIGNAL GENERATOR
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ref_generator is
port(clk,clr: in std_logic;
op: out std_logic);
end ref_generator;
architecture behave of ref_generator is
signal r1: std_logic;
signal r3,dcod,r2: std_logic;
signal cnt: std_logic_vector(7 downto 0);
begin
a: process(clk,clr)
begin
if clr='1' then
r1<='0';
elsif rising_edge(clk) then
r1<= not r1;
end if;
end process a;
b: process(clk,clr)
begin
if clr='1' then
cnt<="00000000";
elsif rising_edge(clk) then
cnt<=cnt+1;
end if;
end process b;
dcod<= (cnt(7) and cnt(6) and (not cnt(5)) and cnt(4) and cnt(3) and cnt(2) and (not cnt(1)) and cnt(0));
c: process(clr,dcod)
begin
if clr='1' then
r2<='0';
elsif rising_edge(dcod) then
r2<= not r2;
end if;
end process c;
d: process(clr,cnt(6))
begin
if clr='1' then
r3<= '0';
elsif rising_edge(cnt(6)) then
r3 <= not r3;
end if;
end process d;
op<= cnt(2);
end behave;
VHDL CODE FOR ENCRYPTOR
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity encrypt is
port(clk,clr: in std_logic;
data_out: out std_logic_vector(63 downto 0);
sel_out: out std_logic_vector(3 downto 0);
original_data: in std_logic_vector(31 downto 0));
end encrypt;
architecture behave of encrypt is
signal pass_code_data: std_logic_vector(11 downto 0);
signal prio_data: std_logic_vector(3 downto 0);
signal din: std_logic_vector(31 downto 0);
signal ad: std_logic_vector(15 downto 0);
signal sel: std_logic_vector(3 downto 0);
begin
din<= original_data;
Counter_as_Selection:process(clk,clr)
begin
if clr='1' then
sel<="0000";
elsif rising_edge(clk) then
sel<= sel+1;
end if;
end process Counter_as_Selection;
sel_out <= sel;
-- Encryption Process
ad(0) <= din(0) xor din(1);
ad(1) <= din(2) xor din(3);
ad(2) <= din(4) xor din(5);
ad(3) <= din(6) xor din(7);
ad(4) <= din(8) xor din(9);
ad(5) <= din(10) xor din(11);
ad(6) <= din(12) xor din(13);
ad(7) <= din(14) xor din(15);
ad(8) <= din(16) xor din(17);
ad(9) <= din(18) xor din(19);
ad(10) <= din(20) xor din(21);
ad(11) <= din(22) xor din(23);
ad(12) <= din(24) xor din(25);
ad(13) <= din(26) xor din(27);
ad(14) <= din(28) xor din(29);
ad(15) <= din(30) xor din(31);
-- Priority informations
priority_selector:process(sel,clr)
begin
if clr='1' then
prio_data<="0000";
else
case sel is
when "0001" => prio_data <= "0100";
when "0010" => prio_data <= "1000";
when "0011" => prio_data <= "0110";
when "0100" => prio_data <= "0011";
when "0101" => prio_data <= "1001";
when "0110" => prio_data <= "1010";
when "0111" => prio_data <= "0010";
when "1000" => prio_data <= "0001";
when "1001" => prio_data <= "1100";
when "1010" => prio_data <= "1111";
when "1011" => prio_data <= "1110";
when "1100" => prio_data <= "1011";
when "1101" => prio_data <= "0101";
when "1110" => prio_data <= "0111";
when others => prio_data <= "1101";
end case;
end if;
end process priority_selector;
-- PASSCODE_GENERATOR
PASSCODE_GENERATOR:process(sel)
begin
if clr='1' then
pass_code_data<="000000000000";
else
case sel is
when "0001" => pass_code_data <= ("0100")&("1111")&("0100" XOR "1111");
when "0010" => pass_code_data <= "1000"&"1111"& ("0100" XOR "1111");
when "0011" => pass_code_data <= "0110"&"1111"& ("0100" XOR "1111");
when "0100" => pass_code_data <= "0011"&"1111"& ("0100" XOR "1111");
when "0101" => pass_code_data <= "1001"&"1111"& ("0100" XOR "1111");
when "0110" => pass_code_data <= "1010"&"1111"& ("0100" XOR "1111");
when "0111" => pass_code_data <= "0010"&"1111"& ("0100" XOR "1111");
when "1000" => pass_code_data <= "0001"&"1111"& ("0100" XOR "1111");
when "1001" => pass_code_data <= "1100"&"1111"& ("0100" XOR "1111");
when "1010" => pass_code_data <= "1111"&"1111"& ("0100" XOR "1111");
when "1011" => pass_code_data <= "1110"&"1111"& ("0100" XOR "1111");
when "1100" => pass_code_data <= "1011"&"1111"& ("0100" XOR "1111");
when "1101" => pass_code_data <= "0101"&"1111"& ("0100" XOR "1111");
when "1110" => pass_code_data <= "0111"&"1111"& ("0100" XOR "1111");
when others => pass_code_data <= "1101"&"1111"& ("0100" XOR "1111");
end case;
end if;
end process PASSCODE_GENERATOR;
data_out<= ad & prio_data & pass_code_data & original_data;
end behave;
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