VHDL implementation of Reversible Logic Gate

We have recently done a PHD Project based on reversible logic gate, FREDKIN Gate is used to configure the Digital Frequency Generator, some of the idea i am sharing here.

Reversible Logic FREDKIN GATE - VHDL CODE

Library ieee;   
use IEEE.std_logic_1164.all;
use IEEE.numeric_bit.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_signed.all;


ENTITY CNTFET_FG IS
port(a,b,c: in std_logic;
p,q,r: out std_logic);   
END  CNTFET_FG;

ARCHITECTURE BEHAVE OF CNTFET_FG IS
BEGIN
FREDKIN_GATE:process(a,b,c)
begin
p<= a;
q<= ((not a) and b) OR (a and c);
r<= (a and b) OR ( (not a) and c);
end process FREDKIN_GATE;
END BEHAVE;   

SIMULATION RESULT - FREDKIN GATE ACT AS AND GATE




FULL INTEGRATION 
 




Learning Continues.....
M.DivyaRamkumar
Sr.VLSI Design Engineer & Consultant
qmostech@gmail.com