VHDL ENTITY
The vhdl code starts with the entity declaration and architecture declaration
Entity is nothing but the black box of the digital module going to be designed
It tells us the input ports and output ports configurations
It also contains the info about external connections to the other modules
There are input ports which is refered as IN , output ports which is referred as OUT and inbetween INOUT port also there where the signal act as input as well as output
Entity starts with a key word ENTITY, label can be any user defined name
A simple VHDL Example how to write entity is shown below
SYNTAX
ENTITY <ENTITY NAME> IS
PORT(input output declarations.......)
END ENTITY<ENTITY NAME>;
Example
ENTITY and_gate IS
PORT(a,b : IN STD_LOGIC;
c :OUT STD_LOGIC);
END ENTITY<ENTITY NAME>;
Hope it is Useful !!
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