Simple Source Code in VHDL for a Clock Divider
-- LIBRARY DECLARATION
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
-- ENTITY DECLARATION
Entity clkdiv is
port(clk,clr: in std_logic;
divided_clock: out std_logic);
end entity clkdiv;
architecture behave of clkdiv is
signal tclk: std_logic;
begin
Clock_divider_Block:process(clk,clr)
begin
if clr='1' then
tclk <='0';
elsif rising_edge(clk) then
tclk<= not tclk;
end if;
end process Clock_divider_Block;
-- output
divided_clock <= tclk;
end behave;
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