Truncated Multiplier VHDL code and results

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CODE

Library ieee;
use ieee.std_logic_1164.all;

entity trunc_mul is
port(
a,b: in std_logic_vector(7 downto 0);
pout:out std_logic_vector(7 downto 0));
end entity trunc_mul;

architecture behave of trunc_mul is

COMPONENT fa is
port(p,q,r: in std_logic;
     sum,carry: out std_logic);
end COMPONENT;

COMPONENT multiplicants is
port(a,b: in std_logic_vector(7 downto 0);
m1,m2,m3,m4,m5,m6,m7,m8,m9,m10: out std_logic;
m11,m12,m13,m14,m15,m16,m17,m18,m19,m20: out std_logic;
m21,m22,m23,m24,m25,m26,m27,m28,m29,m30: out std_logic;
m31,m32,m33,m34,m35,m36,m37,m38,m39,m40,m41,m42,m43: out std_logic);
end COMPONENT;

signal n1,n2,n3,n4,n5,n6,n7,n8,n9,n10,n11,n12,n13,n14,n15,n16,n17,n18,n19,n20,n21,n22,n23,n24,n25,n26,n27,n28,n29,n30,n31,n32,n33,n34,n35,n36,n37,n38,n39,n40,n41,n42,n43 : std_logic;


signal s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15,s16,s17,s18,s19,s20,s21,s22,s23,s24,s25,s26,s27,s28: std_logic;

signal c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,c13,c14,c15,c16,c17,c18,c19,c20,c21,c22,c23,c24,c25,c26,c27,c28: std_logic;

signal k: std_logic;
signal c8a,c9a,c10a,c11a,c12a,c13a: std_logic;



begin
   
mul:multiplicants port map(a,b,n1,n2,n3,n4,n5,n6,n7,n8,n9,n10,n11,n12,n13,
n14,n15,n16,n17,n18,n19,n20,n21,n22,n23,n24,n25,n26,n27,n28,n29,n30,
n31,n32,n33,n34,n35,n36,n37,n38,n39,n40,n41,n42,n43);   
   
fa1: fa port map(n1,n2,n3,s1,c1); 
fa2: fa port map(s1,n4,n5,s2,c2);
fa3: fa port map(s2,n6,n7,s3,c3);
fa4: fa port map(s3,n8,n9,s4,c4);
fa5: fa port map(s4,n10,n11,s5,c5);
fa6: fa port map(s5,n12,n13,s6,c6); 
fa7: fa port map(n6,n14,n15,s7,c7);



fa9: fa port map(n17,n18,c1,s8,c8);
fa10: fa port map(s8,n19,c2,s9,c9);
fa11: fa port map(s9,n20,c3,s10,c10); 
fa12: fa port map(s10,n21,c4,s11,c11);
fa13: fa port map(s11,n22,c5,s12,c12);
fa14: fa port map(s12,n23,c6,s13,c13);


fa16: fa port map(n24,n25,c8,s14,c14); 
fa17: fa port map(s14,n26,c9,s15,c15);
fa18: fa port map(s15,n27,c10,s16,c16);
fa19: fa port map(s16,n28,c11,s17,c17);
fa20: fa port map(s17,n29,c12,s18,c18);



fa22: fa port map(n30,n31,c14,s19,c19);
fa23: fa port map(s19,n32,c15,s20,c20);
fa24: fa port map(s20,n33,c16,s21,c21);
fa25: fa port map(s21,n34,c17,s22,c22);


 
fa27: fa port map(n35,n36,c19,s23,c23);
fa28: fa port map(s23,n37,c20,s24,c24);
fa29: fa port map(s24,n38,c21,s25,c25);


fa31: fa port map(n39,n40,c23,s26,c26); 
fa32: fa port map(s26,n41,c24,s27,c27);


fa34: fa port map(n42,n43,c26,s28,c28);

--********************************************************

fa8: fa port map(n16,s7,c13a,p14,p15);
fa15: fa port map(c7,s13,c12a,p13,c13a);
fa21: fa port map(c13,s18,c11a,p12,c12a);
fa26: fa port map(c18,s22,c10a,p11,c11a);
fa30: fa port map(c22,s25,c9a,p10,c10a);
fa33: fa port map(c25,s27,c8a,p9,c9a);
fa35: fa port map(c27,s28,k,p8,c8a);
--------------------------------------------------------------------- 
k<='1';

pout(0)<=p8;
pout(1)<=p9;
pout(2)<=p10;
pout(3)<=p11;
pout(4)<=p12;
pout(5)<=p13;
pout(6)<=p14;
pout(7)<=p15;

signal p8,p9,p10,p11,p12,p13,p14,p15
end behave;   

RESULTS

 

 

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