Design and implementation of fault tolerant and fault correcting Spintronic Flip flop

Design and implementation of fault tolerant and fault correcting Spintronic Flip flop

Overview of Existing System

With technology down scaling, static power has become one of the biggest challenges in a system on chip. Normally off computing using nonvolatile (NV) sequential elements is a promising solution to address this challenge. Recently, many NV shadow flip-flop architectures have been introduced in which magnetic tunnel junction (MTJ) cells are employed as backup storing elements. Due to the emerging fabrication processes of magnetic layers, MTJs are more susceptible to manufacturing defects than their CMOS counterparts. Moreover, unlike memory arrays that can effectively be repaired with well-established memory repair and coding schemes, flip-flops scattered in the layout are more difficult to repair. Therefore, without effective defect and fault tolerance for NV flip-flops, the manufacturing yield will be affected severely. In this paper a fault-tolerant NV latch (FTNV-L) design, in which several MTJ cells are arranged in such a way that it is resilient to various MTJ faults. The simulation results show that our proposed FTNV-L can effectively tolerate all single MTJ faults with a considerably lower overhead than traditional approaches.

Proposed System

Design of fault tolerant and fault correcting Spintronic Flip flop is implemented here with active dynamic fault correcting scheme. The design implies in such a way that it can able to detect as well as correct the errors occur due to junction tunneling. The internal resistance and capacitance even though plays a protective block for leakage of current and voltages, the junction leakages are happens beyond that. The leakage of current produces power dissipation in the form of heat. The architecture is designed in such a way it will avoid slow leakage faults.

Software required

Language                                       :        VHDL

Simulation Tool : MODELSIM 6.3G,QUARTUS || ,XILINX ISE, MICROWIND

 


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VHDL CODE FOR GATES

VHDL CODE FOR GATES

To become a VLSI designer you should be strong in Digital electronics so keep on learning digital logic and ideas.  Normally in digital electronics two broad catagories of logics we can tell, Combinational circuits and Sequential circuits.

Combinational Logics or Circuits
Combinational logics are logics in which the outputs depends upon present inputs only
examples of combinational circuits are Gates, adders,subtractors,multiplexers,de-multiplexers etc

Sequential Circuits
Sequential Circuits are logics in which the output depends upon present as well as past outputs
examples of sequential circuits are Flipflops , latches, counters etc

Let us start learning from Combinational circuits from Here

Here i give you a Sample VHDL code for combinational Gates

VHDL Code for Logical gates

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

entity gate is
port(a,b: in std_logic;
y1,y2,y3,y4,y5,y6,y7: out std_logic);
end entity gate;

architecture behave of gate is
begin
-- AND GATE
 y1 <= a and b;
--OR GATE
 y2 <= a or b;
--NOT GATE
 y3 <= not a;
--XOR GATE
 y4 <= a xor b;
--XNOR GATE
y5 <= a xnor b;
end behave;

Simple Tools  used for Verifying the Code

MODELSIM 6.3G ALTERA version tool is useful for simply running the code
else you can use XILINX ISE for simulating the code

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