VHDL CODE FOR GATES

VHDL CODE FOR GATES

To become a VLSI designer you should be strong in Digital electronics so keep on learning digital logic and ideas.  Normally in digital electronics two broad catagories of logics we can tell, Combinational circuits and Sequential circuits.

Combinational Logics or Circuits
Combinational logics are logics in which the outputs depends upon present inputs only
examples of combinational circuits are Gates, adders,subtractors,multiplexers,de-multiplexers etc

Sequential Circuits
Sequential Circuits are logics in which the output depends upon present as well as past outputs
examples of sequential circuits are Flipflops , latches, counters etc

Let us start learning from Combinational circuits from Here

Here i give you a Sample VHDL code for combinational Gates

VHDL Code for Logical gates

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

entity gate is
port(a,b: in std_logic;
y1,y2,y3,y4,y5,y6,y7: out std_logic);
end entity gate;

architecture behave of gate is
begin
-- AND GATE
 y1 <= a and b;
--OR GATE
 y2 <= a or b;
--NOT GATE
 y3 <= not a;
--XOR GATE
 y4 <= a xor b;
--XNOR GATE
y5 <= a xnor b;
end behave;

Simple Tools  used for Verifying the Code

MODELSIM 6.3G ALTERA version tool is useful for simply running the code
else you can use XILINX ISE for simulating the code

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