Expected Energy Optimization for Real-Time Multiprocessor SoCs Running Periodic Tasks with Uncertain Execution Time

Design of energy-saving optimization approach for Multi-processor SoC task scheduling

Power saving is a challeging task in VLSI design perhaps the multiple processing SOC carry out more power consumption through system on chip model. 

The low power VLSI architecture is capable of handling the leakage power within the circuit by altering the circuit level changes we call it as optimization.

Multi processor SOC architectures required optimized SOC systems with stable operating clock frequency.

The SoC blocks are composed of FSM enabled pipelines control mechanism. the prioritizing algorithm that holds various SOC modules put priority in the index thus handle the modules one by one without interrupting the other modules. 

The best SOC platform also capable of handling the uncertain exceutions in the system architecture by providing safegaurd module as error monitor. the dynamic error monitor keep tracks the glitches and stack the pulses to produce recycled clock with stable Duty Cycle

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