A Smaller, Faster, and More Energy-Efficient Complementary STT-MRAM Cell Uses Three Transistors and a Ground Grid: More Is Actually Less

Design of STT-MRAM using reversible Logic FredKin Gates

Abstract

The existing paper focusing on the lower level caches, shows an improved 3T 2MTJ cell with a ground grid and a novel three transistor read and write operation to improve area density, sense margin, write performance, and write energy consumption. Despite the cell’s three transistors, the improved array configuration reduces the cell area by 22% as compared with the 2T 2MTJ cell, making it only 55% larger than a 1T 1MTJ cell. The novel mismatch tolerant read operation uses all three transistors and increases the sense margin by up to 88%. The novel variation resilient write operation also uses all three transistors and takes advantage of the inherent MTJ characteristics and complementary operation of the cell. This increases the write performance by 2× and reduces the write energy by 3× compared with the 2T 2MTJ cell and by 1.5× compared with the 1T 1MTJ cell.

Existing System

The existing paper focusing on the lower level caches, shows an improved 3T 2MTJ cell with a ground grid and a novel three transistor read and write operation to improve area density, sense margin, write performance, and write energy consumption. Despite the cell’s three transistors, the improved array configuration reduces the cell area by 22% as compared with the 2T 2MTJ cell, making it only 55% larger than a 1T 1MTJ cell. The novel mismatch tolerant read operation uses all three transistors and increases the sense margin by up to 88%.

Proposed System

In the proposed system, low power STT MRAM is designed using reversible logic gates. One of the reversible logic gate is Fredkin gate. The digital architecture of fredkin gate is implemented as module and those can be appliyed for MRAM. Low power architecture is achieved using low power logics such as power gate and clock gate

A High-Efficiency 6.78-MHz Full Active Rectifier With Adaptive Time Delay Control for Wireless Power Transmission

Design of Low power Wireless Multi-DC Converter and Transmitter

Abstract

In the existing paper presents a full active rectifier consisting of GaN devices and a CMOS controller designed for wireless power transmission in high-power consumer devices. An adaptive time delay control circuit is developed to maximize the conduction interval of the GaN switch, which can significantly reduce the power loss caused by the forward voltage imposed by the diode. The Existing control algorithm also eliminates the reverse leakage current of the rectifier, and thus further improves its power transfer efficiency. The controller implemented based on a high voltage 0.18-μm CMOS process and the power stage consisting of four GaN transistors are assembled on the same printed circuit board (PCB) board. The proposed rectifier provides a maximum output current of 3 A at 5 V, with a 6.78-MHz ac input voltage. Its peak power transfer efficiency is 91.8%.

Existing System

The Existing control algorithm also eliminates the reverse leakage current of the rectifier, and thus further improves its power transfer efficiency. The controller implemented based on a high voltage 0.18-μm CMOS process and the power stage consisting of four GaN transistors are assembled on the same printed circuit board (PCB) board. The proposed rectifier provides a maximum output current of 3 A at 5 V, with a 6.78-MHz ac input voltage. Its peak power transfer efficiency is 91.8%.

Proposed System

In the proposed system we are planning to vary the architecture in such a way it will generate multiple DC voltages and transmit the same to various circuits through wireless manner. The design consists of master control unit, communication unit, low power control system. The architecture uses maximum of low power logics such as power gating , clock gating etc. The outcome of the design implies more accurate dc voltages at different levels

A Fully Integrated Discrete-Time Superheterodyne Receiver

Design of configurable superhetrodyne receiver for wireless medical applications

OVERVIEW

The zero/low intermediate frequency (IF) receiver (RX) architecture has enabled full CMOS integration. As the technology scales and wireless standards become ever more challenging, the issues related to time-varying dc offsets, the second-order nonlinearity, and flicker noise become more critical. In the existing paper a new architecture of a superheterodyne RX that attempts to avoid the issues related to time-varying dc offsets. By exploiting discrete-time (DT) operation and using only switches, capacitors, and inverter-based gm-stages as building blocks, the architecture becomes amenable to further scaling. Full integration is achieved by employing a cascade of four complex-valued passive switched-cap-based band pass filters sampled at 4× of the local oscillator rate that perform IF image rejection. Channel selection is achieved through an equivalent of the seventh-order filtering. A new twofold noise-canceling low-noise transconductance amplifier is proposed. Frequency domain analysis of the RX is presented by the proposed DT model. The RX is wideband and covers 0.4–2.9 GHz with a noise figure of 2.9–4 dB. It is implemented in 65-nm CMOS and consumes 48–79 mW.

Existing System

In the existing paper a new architecture of a superheterodyne RX that attempts to avoid the issues related to time-varying dc offsets. By exploiting discrete-time (DT) operation and using only switches, capacitors, and inverter-based gm-stages as building blocks, the architecture becomes amenable to further scaling. Full integration is achieved by employing a cascade of four complex-valued passive switched-cap-based band pass filters sampled at 4× of the local oscillator rate that perform IF image rejection. Channel selection is achieved through an equivalent of the seventh-order filtering.

Proposed System

In the proposed system a configurable VLSI design architecture is being designed in which the superheterodyne receiver is designed purely in digital manner to handle multiple frequency of operation. The design used at various medical applications nowadays medical electronics inventments are more precise and requires more challenging configurations to be done at minimum time for various medical analysis of disease etc The proposed system is used to generate such variable outputs of audio frequencies used at medical equipments.