VHDL Architecture
The structure of VHDL Programming consists of entity and architecture
As explained already , entity is used to define input and output port informations
Architecture tells you the functional behaviour of the Logic which we are writing
One entity can address multiple architecture, whereas multiple entities cannot able to address one architecture, the design structure is not possible
SYNTAX
ARCHITECTURE <NAME> OF <ENTITY_NAME> IS
BEGIN
SEQUENTIAL & COMBINATIONAL LOGIC DECLARATIONS
END <NAME>;
VHDL EXAMPLE
architecture for Half adder:
***********************************************************
architecture half_adder of ha is
begin
sum <= a XOR b;
carry <= a AND b;
end half_adder;
***********************************************************
