Proposed Title
Design of FPGA based
Digitally Controlled LDO for automatic speed control application
Abstract
Digital low-dropout (DLDO) regulators are gaining attention
due to their design scalability for distributed multiple voltage domain
applications required in state-of-the-art system on- chips. Due to the discrete
nature of the output current and the discrete-time control loop, the
steady-state response of the DLDO has inherent output voltage ripple. A hybrid
DLDO (HD-LDO) with fast response and stable operation across a wide load range
while reducing the output voltage ripple is proposed. In the HD-LDO, a DLDO and
a low current analog ripple cancellation amplifier (RCA) work in parallel. The DLDO suppresses the output dc of the RCA within
its current resolution. With this arrangement, a majority of the dc load current
is provided by the DLDO and the RCA supplies ripple cancellation current. The
HD-LDO is designed and fabricated in a 180-nm CMOS technology,
Existing System
In
the existing system In the HD-LDO, a
DLDO and a low current analog ripple cancellation amplifier (RCA) work in
parallel is designed. The DLDO
suppresses the output dc of the RCA within its current resolution. With this
arrangement, a majority of the dc load current is provided by the DLDO and the
RCA supplies ripple cancellation current. The HD-LDO is designed and fabricated
in a 180-nm CMOS technology.
Proposed System
In the proposed system FPGA controlled DLDO is
implemented using Memristor scheme. The memristor is implemented and used for
controlling the DLDO in such a way it produce numerous number of DLDO values to
control the speed of the machines, rotor speed, frequency control , wavelength
etc Here we implement a digital LDO using FPGA for speed control application
