Eliminating Synchronization
Latency Using Sequenced Latching
ABSTRACT
A concept of multicore system is designed which have
a large number of components operating in different clock domains and
communicating through asynchronous interfaces. These interfaces use synchronizer
circuits, which guard against metastability failures but introduce latency in
processing the asynchronous input. In the Existing design a speculative method
that hides synchronization latency by overlapping it with computation cycles. The
accuracy of our approach through a field programmable gate array implementation
and apply it to a number of synthesized benchmarks. Synthesis results reveal
that our approach achieves average savings of 135% and 204% in area costs and
nearly 100% in power costs compared to two similar speculative techniques.
EXISTING SYSTEM
We Design a
speculative method that hides synchronization latency by overlapping it with
computation cycles. We verify the correctness of our approach through a field
programmable gate array implementation and apply it to a number of synthesized benchmarks.
Synthesis results reveal that our approach achieves average savings of 135% and
204% in area costs and nearly 100% in power costs compared to two similar
speculative techniques.
PROPOSED SYSTEM
In the proposed system the sequencing
of latches has been done by designing a control circuit which make the circuit
work depend on the control inputs from the generator. The sequencing my be at
the rising edge of clock or falling edge of the control clock, By doing this we
can reduce lots of elements required for synchronizer and the control circuit
may be done with a few Flip flops.
SOFTWARE REQUIREMENT
Design Environment: XILINX ISE
Language: VHDL
Simulation: MODELSIM / XILINX ISE
Simulator
HARDWARE REQUIREMENT
XILINX SPARTAN Development Board
Device: XC3S500E
