DESIGN & IMPLEMENTATION OF POWER
SAVING SYNTHESIZER
Introduction
o Design of Low power energy saving
digital circuit is realized here
o Design of Frequency synthesizer designed
as a application is established using low power logics
o The architecture is designed in such a
way the power dissipation can be avoided during static mode as well as dynamic
mode
Existing
System
•
In the existing system, Multiplexer is designed
• Leakage of
power is analyzed
• Power
leakage due to capacitance is analyzed
Proposed System
• In the proposed
system design of application module Frequency synthesizer is realized here
• Design
architecture is design with Low power circuits to reduce power
• The proposed
design also contains leakage avoidance circuits to save resource
Literature Survey
Title
Statistical Analysis and Optimization for Timing and Power
of VLSI
Author
By L Cheng – 2010
Analysis On: Deterministic Device and Architecture Co-
Optimization for FPGA Power,. Delay, and Area
Minimization., tells that the gate delay as linear functions
of variation sources and assumed all the variation sources are by leakage
sources
Title
Reduction of Power Consumption in FPGAs
Author
N Grover - 2012 Analysis on :
Low power digital modules to reduce the power dissipation
and review the work carried out in this area and The programming technology for
the logic and interconnect resources can be.
Problem Formulation
• Leakage
power due to transient effect in transistor switching
• Leakage of
power due to unused logics and area utilized by the same
Objective
•
To design a low power architecture for Frequency synthesizer using Low power
techniques
•
To design a unused power wastage avoidance circuit to utilize the power
efficiently
Design Block diagram
Advantages
• High speed
design with power saving modules
• Low power
circuits with area efficient architecture
• Reliable
code and code reusability
Applications
• High speed modems
• Real time wireless
networks
• Communication systems
• Medical equipments
