VHDL implementation of Reversible Logic Gate

We have recently done a PHD Project based on reversible logic gate, FREDKIN Gate is used to configure the Digital Frequency Generator, some of the idea i am sharing here.

Reversible Logic FREDKIN GATE - VHDL CODE

Library ieee;   
use IEEE.std_logic_1164.all;
use IEEE.numeric_bit.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_signed.all;


ENTITY CNTFET_FG IS
port(a,b,c: in std_logic;
p,q,r: out std_logic);   
END  CNTFET_FG;

ARCHITECTURE BEHAVE OF CNTFET_FG IS
BEGIN
FREDKIN_GATE:process(a,b,c)
begin
p<= a;
q<= ((not a) and b) OR (a and c);
r<= (a and b) OR ( (not a) and c);
end process FREDKIN_GATE;
END BEHAVE;   

SIMULATION RESULT - FREDKIN GATE ACT AS AND GATE




FULL INTEGRATION 
 




Learning Continues.....
M.DivyaRamkumar
Sr.VLSI Design Engineer & Consultant
qmostech@gmail.com

VLSI Design Solutions

VLSI Design Solutions:

Very large scale integration design is not at a simple one in the present industry needs.

Starting from Transistor era, Improvements held in integrated Chips are wide range. Some of the factors includes 

• Improving the transistor Size
• Reducing the Power consumption
• Reducing the leakage current and other transient issues
• Improving Wafer Quality

Likewise the day by day improvements are in wide range.

To achieve such factors, our engineers underwent so many test procedures and experiments.Resultant only what we are seeing today the huge development of ASICs in all products which works high speed.

Yes , Speed of operation plays a major role in ASIC industry.

Even though so many challenges approaches VLSI Design, the improvements and developments in the Chip design industry grown rapidly because of Very Large scale integration.

Efficient usage of Logic cells and creating innovative logic given a clear view of VLSI Design solutions.

Learning Continues

DivyaRamkumar

Sr.VLSI  Design Engineer & Consultant

qmostech@gmail.com

VLSI Design and implementation of Built in Self Test

VLSI Design and implementation of Built in Self Test 

MODULE 1: Design of Test Pattern Generator (TPG)

DESCRIPTION:

          The  test pattern generation is the basic module for Analog built-in self-test(BIST).In the proposed system a Built in self test is performed using a sample module which is nothing but a random access memory(RAM) is designed. The BIST RAM is considered under test and difference advanced test cases are given to test the circuit. We are using the test pattern generator for applying the proper test cases to the BIST RAM. 

MODULE 2:  Design of control unit

DESCRIPTION:

          This module is implemented for controlling the overall operations in the RAM built-in self-test. The control unit makes the control over the writing, reading, addressing and comparison etc. in the built-in self-test. Moreover the control unit will take the decision about the process in the BIST.In this way improves the efficiency.

MODULE 3: Design of Test Pattern Recorder (TPR)

DESCRIPTION:

               In the RAM built-in self-test, the input data to be stored in the RAM memory locations. The comparator in the BIST (built-in self-test) system take the data from the RAM module and also directly from the input with the help of BIST controller. After the comparison we get the output with respect to the inputs of comparator and test the BIST RAM under the different advanced test cases. The performance is measure in such a way the power consumption reduction, Area efficiency is achieved.

MODULE 4: Design and analysis of Integration module

DESCRIPTION:

                   We are integrating all the sub modules and output signals are routed into the required ports as per the FPGA device.

best vlsi projects in chennai : Robust Secure Scan Design Against Scan-Based Differential Cryptanalysis

Robust Secure Scan Design Against Scan-Based

Differential Cryptanalysis

Objective:     

     The objectives of this proposed architecture to design Robust Secure Scan Design countermeasure Against Scan-Based Differential Cryptanalysis for compatible with the state-of-the-art design flow.

Existing system:

   Existing technology Scan chains have exploited to develop attacks on cryptographic hardware and steal intellectual properties from the chip. This paper proposed a secured strategy to test designs by inserting a certain number of inverters between randomly selected scan cells. The security of the scheme has been analyzed. Two detailed case studies of RC4 stream cipher and AES block cipher have been presented to show that the proposed strategy prevents existing scan-based attacks in the literature. The elegance of the scheme lies in its less hardware overhead.

Disadvantage:

• Ø It is not applicable in case that the secret key is hardware wired
•  
• Ø The reset operation cannot clear and should not clear them

 

Proposed System:

       A robust secure scan (RSS) is proposed in this paper, in which a new kind of scan flip-flop, called robust secure scan flip-flop (RSSF), is introduced from a security aspect. By including such RSSFs into crypto cores, all the advantages and simplicity of traditional scan test are preserved, and the security is significantly improved with ignorable design and test overhead.

Advantages:

Ø The security is significantly improved.

Application:

Ø Encryption is used to (attempt to) ensure security in communication

Ø Most current secrecy systems for transmission use a private key system for transforming transmitted information because it is the fastest method that operates with reasonable assurance and low overhead.