A Smaller, Faster, and More Energy-Efficient Complementary STT-MRAM Cell Uses Three Transistors and a Ground Grid: More Is Actually Less

Design of STT-MRAM using reversible Logic FredKin Gates

Abstract

The existing paper focusing on the lower level caches, shows an improved 3T 2MTJ cell with a ground grid and a novel three transistor read and write operation to improve area density, sense margin, write performance, and write energy consumption. Despite the cell’s three transistors, the improved array configuration reduces the cell area by 22% as compared with the 2T 2MTJ cell, making it only 55% larger than a 1T 1MTJ cell. The novel mismatch tolerant read operation uses all three transistors and increases the sense margin by up to 88%. The novel variation resilient write operation also uses all three transistors and takes advantage of the inherent MTJ characteristics and complementary operation of the cell. This increases the write performance by 2× and reduces the write energy by 3× compared with the 2T 2MTJ cell and by 1.5× compared with the 1T 1MTJ cell.

Existing System

The existing paper focusing on the lower level caches, shows an improved 3T 2MTJ cell with a ground grid and a novel three transistor read and write operation to improve area density, sense margin, write performance, and write energy consumption. Despite the cell’s three transistors, the improved array configuration reduces the cell area by 22% as compared with the 2T 2MTJ cell, making it only 55% larger than a 1T 1MTJ cell. The novel mismatch tolerant read operation uses all three transistors and increases the sense margin by up to 88%.

Proposed System

In the proposed system, low power STT MRAM is designed using reversible logic gates. One of the reversible logic gate is Fredkin gate. The digital architecture of fredkin gate is implemented as module and those can be appliyed for MRAM. Low power architecture is achieved using low power logics such as power gate and clock gate