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VLSI IMPLEMENTATION OF  CLOCK MISBEHAVE  REDUCTION TECHNIQUE  FOR LOGIC GATES

Overview of existing system

In existing system, soft error tolerance achieved by selective transistor redundancy for combinational circuits. Transistors have protected based on duplicating and sizing a subset of transistors necessary for providing the protection.LGSynth’91 benchmark circuits used in existing system

Existing system

Soft errors generated   due to energetic particle strike  in  CMOS transistor. Protection scheme partially reduced energetic particle strike effect .remaining soft error  have been decreased by  increasing  output capacitance  and reducing output resistance.fault tolererance technique implemented in NAND gate

Proposed system

The soft error reduction technique is reduced by replacing the active  XNOR gate and XOR  gate in the places of where the misbehave of clock pulses need to be avoided. The clock errors are mainly due to minimal and continuous accumulation of delays added up and which behave like trigger the clock phase at one stage. The action may be simply a small one but residual accumulation of the delay generate a huge clock delay at one stage. This may change or trigger the other circuits too. Because of  energetic particle injection when diffusion, soft errors like  stuck at 0 fault and stuck at 1 fault   is occurred  in transistor level too. In the proposed system we are planning to implement a avoidance circuit for all other errors too.

Simulation Tool

MODELSIM

Implementation tools

XILINX

Analysis Tools