How to write a simple VHDL Code?

VLSI projects in Chennai :

How to write a simple VHDL Code:

• Writing a VHDL Code become easy when you are more aware about how the digital elements are working.
• Digital Elements in the sense i am meaning that digital logic such as gate,flip flops,adders, counter etc
• In all the digital circuits the most important input element is the clock and global reset or we call it as Hardware reset
• Before writing a vhdl code for any digital circuit first keep in mind about the flow of clock and control of reset 
• In my upcoming post i will teach you how to handle those clocks and reset in best way
• For writing a VHDL code for simple clocked D-flip flop, you need the inputs clock, reset, input d and output q, qbar
• First plan for a Truth table which will help you understand the input outputs or understand the waveforms or we call it as timing diagram
• for a simple d-flip flop, the output may be ZERO or ONE which depends upon either the rising edge of the clock or falling edge of the clock
• Consider if its rising edge, for every rising edge of the clock signal, the input d is kept open ported which means whatever signal input available at D is transferred to q output 
• The invert of the q is qbar which is also triggered at every rising edge of the clock

Consider the Logic circuit below & Equivalent code too

 

CODE:

< Write Library file >

architecture behave of dff is

begin

dff_block:process(clk,rst)
begin
if rst='1' then
 q<='0';
qbar<='0';
elsif rising_edge(clk) then
q<=d;
qbar<=not d;
end if;
end process dff_block;
end architecture behave;


This is just a simple way of writing a vhdl code for Dflip flop

Key points about D-ff

• Edge sensitive device
• Used as a Buffer in fast flowing data path
• Used as gated flip flop where glitches occurs
• Low power device
• Helpful for generating clocks by designing counters

 

For more details & sample codes help contact us!!!

Energy Conservation and Contribution of EDA tools in VLSI

Energy Conservation and Contribution of EDA tools in VLSI


Energy conservation is one of the biggest factor nowadays and future to be discussed everywhere since the demand on electricity is more like from here to the next upcoming years the amount of electricity required will be keep on increasing.

People started consuming the energy in a limited scale and where it cannot be limited that much in industrial or commercial places.

Demand on electricity increases day by day causes the lack of electricity distribution in urban areas

Technological inventments research and development although allow so many interesting concepts on analysing the energy usage and controlling the same in a smarter way

EDA tools and internet development enhance the research in the wider range in india

LED technology is increasing day by day to reduce the power consumption, Led lights, led sense panels,Led for controls become more applicable everywhere

A research on LED for internet also on the future path, people encouraging the low power modules always

Eda tools plays a major role in developing such new investment also enable the engineers to think in a creative way

VLSI technology support the latest EDA tools for faster processing , high speed of operational keya, more configurable features and flexible user inputs

VLSI design provides the engineers the freedom on thinking the creative logic hence its still more demanding
domain always.

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Design of FPGA based Digitally Controlled LDO for automatic speed control application

CODE QM01:

Design of FPGA based Digitally Controlled LDO for automatic speed control application 

Project Highlights

• VHDL code is used to design a LDO architecture
• Simulation Result shows Digital LDO Performance & Control signals
• Output contains 5 modules 
• 12 different clock outputs added up provides weightage to project
• IEEE Paper implementation  Power , area result in XILINX

COST 4500/-
Contact for more details CLICK HERE

Output Screenshot

me project support new ieee 2017 topic

vlsi projects in chennai

VLSI IMPLEMENTATION OF  CLOCK MISBEHAVE  REDUCTION TECHNIQUE  FOR LOGIC GATES

Overview of existing system

In existing system, soft error tolerance achieved by selective transistor redundancy for combinational circuits. Transistors have protected based on duplicating and sizing a subset of transistors necessary for providing the protection.LGSynth’91 benchmark circuits used in existing system

Existing system

Soft errors generated   due to energetic particle strike  in  CMOS transistor. Protection scheme partially reduced energetic particle strike effect .remaining soft error  have been decreased by  increasing  output capacitance  and reducing output resistance.fault tolererance technique implemented in NAND gate

Proposed system

The soft error reduction technique is reduced by replacing the active  XNOR gate and XOR  gate in the places of where the misbehave of clock pulses need to be avoided. The clock errors are mainly due to minimal and continuous accumulation of delays added up and which behave like trigger the clock phase at one stage. The action may be simply a small one but residual accumulation of the delay generate a huge clock delay at one stage. This may change or trigger the other circuits too. Because of  energetic particle injection when diffusion, soft errors like  stuck at 0 fault and stuck at 1 fault   is occurred  in transistor level too. In the proposed system we are planning to implement a avoidance circuit for all other errors too.

Simulation Tool

MODELSIM

Implementation tools

XILINX

Analysis Tools

Challenges in VLSI projects

Vlsi projects in chennai

 Challenges in VLSI Projects

VLSI Design is a unique domain where engineering peoples can learn a lot of creativity day by day

The demand for vlsi projects in chennai and other places increased more because of the domain knowledge curiocity

Peoples are having lots of challenges in developing vlsi projects, In the final year projects vlsi projects give you more weightage

VLSI developing peoples must be a all rounder, since they have to focus on all kinds of area in electronics in digital and analog too

People should be interested in developing new creative ideas to enhance the principle output

Digital electronics is the core idea required to be involved in developing VLSI projects

VLSI projects in chennai for ieee final year implementation gives you unique knowledge on digital computations and logical thinking

Creating logical ideas for existing circuits can be the challenge

Developing optimized code with low power logic also be the challenge

Creativity is the challenge in lots of analog concepts too

But learning will be the key part of vlsi projects design which gives you unique idea about the core area.

Keep researching !!!

Hope its useful....

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ME project excellence guidance

ME Mtech Projects guidance

Students undergoing ME projects should take up the project work as two different phases.

ME student first select the research paper through Phd staff or directly from IEEE website

The selected paper should be analysed better through literature review of previous works

The previous year paper may contain the problem analysis and report

The existing paper also contain future enhancing possibility hints

The Me students should review the paper well and they need to find out problem analysis

During phase 1 the students can develop the solutions for present problem found.

During the phase 2 of project work they can either modify the algorithm or they can develop the application related to that present findings.

Analysis report, Simulation report, and result validation is very important for the work

Finally they need to present a paper using generated results.

Involvement in present work helpful for them to start their research work in PhD.

Keep Researching...

phd projects in chennai :Design and implementation of auto-tunable index for memory mapping in FPGA Devices using MEMRISTOR

Design and implementation of auto-tunable index for memory mapping in FPGA Devices using MEMRISTOR

Module Description

Module 1: Design of Memory under Test (MUT)

This module consists of digital memory unit which contains all the memory operations such as memory read, memory write, memory store and chip selection. Read clock and write clocks are generated in the same module itself

Module 2: Design of Auto-Tunable index Control

This module consists of configurable tuning inputs to control the memory index operations, these inputs are generated automatically using the clock controlled counter. Also consists of control signals and reference signals to control the major operations internally, all the internal signals also displayed in to the simulation window

Module3: Design of Memristors control

This module shows how the memristors works and the memristance is generated. Auto mode and manual mode are the optional things given for tuning. The tuning resolution can be varied at any time by simple code modifications.

Module 4: Integration

This module is used to integrate the sub systems with the main module