PRJ 08
Design and
implementation of fault tolerant and fault correcting Spintronic Flip flop
Overview of Existing System
With technology down scaling, static power has become
one of the biggest challenges in a system on chip. Normally off
computing using nonvolatile (NV) sequential elements is a promising solution to
address this challenge. Recently, many NV shadow flip-flop architectures have
been introduced in which magnetic tunnel junction (MTJ) cells are
employed as backup storing elements. Due to the emerging fabrication processes
of magnetic layers, MTJs are more susceptible to manufacturing defects than
their CMOS counterparts. Moreover, unlike memory arrays that can effectively be
repaired with well-established memory repair and coding schemes, flip-flops
scattered in the layout are more difficult to repair. Therefore, without
effective defect and fault tolerance for NV flip-flops, the manufacturing yield
will be affected severely. In this paper a fault-tolerant NV latch (FTNV-L)
design, in which several MTJ cells are arranged in such a way that it is
resilient to various MTJ faults. The simulation results show that our proposed FTNV-L
can effectively tolerate all single MTJ faults with a considerably lower
overhead than traditional approaches.
Proposed System
Design
of fault tolerant and fault correcting Spintronic Flip flop is implemented here
with active dynamic fault correcting scheme. The design implies in such a way
that it can able to detect as well as correct the errors occur due to junction
tunneling. The internal resistance and capacitance even though plays a
protective block for leakage of current and voltages, the junction leakages are
happens beyond that. The leakage of current produces power dissipation in the
form of heat. The architecture is designed in such a way it will avoid slow
leakage faults.
existing block diagram
Proposed Modified diagram
