Configurable FFT using mixed radix
form
Module
1: Design of FFT Block
The FFT computation is accomplished in three stages. The x(0) until x(15)
variables are denoted as the input values for FFT computation and X(0) until
X(15) are denoted as the outputs. The pipeline architecture of the 16 point FFT
is shown in Fig 4.1 consisting of butterfly schemes in it. There are two
operations to complete the computation in each stage. Which is implemented in
the FFT BLOCK.
Module 2: Design of
Control unit
FFT Computation can be controlled using a software controlled finite state
machine control algorithm written in VHDL.Reference signals are used to control
the data flow and address flow.
Module 3: Design of
adder & Subtractor section
This module consists of adder and subtractor sections used for calculating
the fft co-efficients. Here in our project we have a single adder and using
timing control the number of adder can be reduced.
Module 4: Design of
Integration module
This module consists of integration of sub modules with respect to clock
and other synchronization procedures are done over here.
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