A Low-Complexity Turbo Decoder Architecture
for
Energy-Efficient Wireless Sensor Networks
Abstract:-
Energy constrained
wireless communication applications realization is done here, to facilitate low
transmission energy consumption, reduce the overall energy consumption; lookup
table-log-BCJR (LUT-Log-BCJR) architectures having low processing energy consumption are required. In
this existing design, we decompose the LUT-Log-BCJR architecture into its most fundamental
add compare select (ACS) operations and perform them using a novel
low-complexity ACS unit. We demonstrate that our architecture employs an order of magnitude
fewer gates than the most recent LUT-Log-BCJR architectures, facilitating a 71%
energy consumption reduction. Compared to state-of-the-art maximum logarithmic
Bahl-Cocke-Jelinek-Raviv implementations, our approach facilitates a 10%
reduction in the overall energy consumption at ranges above 58 m.
Existing
System:-
In this
existing design, we implemented the LUT-Log-BCJR architecture into its most
fundamental add compare select (ACS) operations and perform them using a novel
low-complexity ACS unit. The demonstration also simulates the energy
efficiency, and power reduction as shown in this paper.
Proposed
System:-
In the proposed system the LUT log BCJR is
designed with Clock gating technique which leads to reduction in Power
consumption and energy consumption reduction is carried out. The circuit is
converted into digital hardware.
Module Description
Module 1: Design of
Software Requirements:-
Design
Environment: XILINX ISE
Language:
VHDL
Simulation:
MODELSIM / XILINX ISE Simulator
Hardware Requirements’:-
XILINX
SPARTAN Development Board
Device:
XC3S500E
