VLSI Projects in Chennai

VLSI PROJECTS – IEEE 2017

·       Scan Chain Masking for Diagnosis of Multiple Chain Failures in a Space Compaction Environment

·       TM-RF: Aging-Aware Power-Efficient Register File Design for Modern Microprocessors

·       A Fault Detection and Tolerance Architecture for Post-Silicon Skew Tuning

·       PAQCS: Physical Design-Aware Fault-Tolerant Quantum Circuit Synthesis

·       An MPCN-Based BCH Codec Architecture With Arbitrary Error Correcting Capability

·       An Efficient SRAM Yield Analysis and Optimization Method With Adaptive Online Surrogate Modeling

·       New Analytic Model of Coupling and Substrate Capacitance in Nanometer Technologies

·       A 110-nm CMOS 0.7-V Input Transient-Enhanced Digital Low-Dropout Regulator With 99.98% Current Efficiency at 80-mA Load

·       Multicore SIMD ASIP for Next-Generation Sequencing and Alignment Biochip Platforms

·       An 8-bit 0.35-V 5.04-fJ/Conversion-Step SAR ADC With Background Self-Calibration of Comparator Offset

·       A Holistic Analysis of Circuit Performance Variations in 3-D ICs With Thermal and TSV-Induced Stress Considerations

·       On the Efficacy of Through-Silicon-Via Inductors

·       Direct Period Synthesis for Achieving Sub-PPM Frequency Resolution Through Time Average Frequency: The Principle, The Experimental Demonstration, and Its Application in Digital Communication

·       Background Digital Calibration of Comparator Offsets in Pipeline ADCs

·       A High-Performance On-Chip Bus (MSBUS) Design and Verification

·       VLSI Design for SVM-Based Speaker Verification System

·       A Ring-Oscillator-Based Reliability Monitor for Isolated Measurement of NBTI and PBTI in High-k/Metal Gate Technology

·       Design and Analysis of Highly Energy/Area-Efficient Multiported Register Files With Read Word-Line Sharing Strategy in 65-nm CMOS Process

·       Trip-Point Bit-Line Precharge Sensing Scheme for Single-Ended SRAM

·       A Semiblind Digital-Domain Calibration of Pipelined A/D Converters via Convex Optimization

·       Corrections to “Super Fast Physics-Based Methodology for Accurate Memory Yield Prediction”

 

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