LIST OF LATEST VLSI PROJECTS AVAILABLE
IEEE 2017 –
VLSI TITLES
1.
A
Fully Integrated Discrete-Time Super heterodyne Receiver
2.
An
FPGA-Based Hardware Accelerator for Traffic Sign Detection
3.
Performance
Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit
4.
STT-RAM
Buffer Design for Precision-Tunable General-Purpose Neural Network Accelerator
5.
Deep
Convolutional Neural Network Architecture With Reconfigurable Computation
Patterns
6.
A
65-nm CMOS Constant Current Source With Reduced PVT Variation
7.
Design
of Power and Area Efficient Approximate Multipliers
8.
A
High-Efficiency 6.78-MHz Full Active Rectifier With Adaptive Time Delay Control
for Wireless Power Transmission
9.
A
100-mA, 99.11% Current Efficiency, 2-mVpp Ripple Digitally Controlled LDO With
Active Ripple Suppression
10.
VLSI
Extreme Learning Machine: A Design Space Exploration DRAM-Based Intrinsic
Physically Unclonable Functions for System-Level Security and Authentication
11.
RoBA
Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet
Energy-Efficient Digital Signal Processing
12.
A
110-nm CMOS 0.7-V Input Transient-Enhanced Digital Low-Dropout Regulator With
99.98% Current Efficiency at 80-mA Load
13.
A
High-Speed and Power-Efficient Voltage Level Shifter for Dual-Supply
Applications
14.
A
6-mW, 70.1-dB SNDR, and 20-MHz BW Continuous-Time Sigma-Delta Modulator Using
Low-Noise High-Linearity Feedback DAC
15.
10T
SRAM Using Half- VDD Precharge and Row-Wise Dynamically Powered Read Port for
Low Switching Power and Ultralow RBL Leakage
16.
A
Smaller, Faster, and More Energy-Efficient Complementary STT-MRAM Cell Uses
Three Transistors and a Ground Grid: More Is Actually Less
17.
Dual-Quality
4:2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers
18.
High-Current
Drivability Fibonacci Charge Pump With Connect-Point-Shift Enhancement
19.
High-Throughput
and Energy-Efficient Belief Propagation Polar Code Decoder
20.
Silicon
Demonstration of Hardware Trojan Design and Detection in Wireless Cryptographic
ICs
21.
Streaming
Elements for FPGA Signal and Image Processing Accelerators
22.
A
50-mA 99.2% Peak Current Efficiency, 250-ns Settling Time Digital Low-Dropout
Regulator With Transient Enhanced PI Controller
23.
A
Capacitor-Less LDO With High-Frequency PSR Suitable for a Wide Range of On-Chip
Capacitive Loads
24.
Hardware
Implementation for Real-Time Haze Removal
25.
A
16-Core Voltage-Stacked System With Adaptive Clocking and an Integrated
Switched-Capacitor DC–DC Converter
26.
Resource-Efficient
SRAM-Based Ternary Content Addressable Memory
27.
Novel
Radiation-Hardened-by-Design (RHBD) 12T Memory Cell for Aerospace Applications
in Nanoscale CMOS Technology
28.
Power-Gated
9T SRAM Cell for Low-Energy Operation
29.
A
170-dB Ω CMOS TIA With 52-pA Input-Referred Noise and 1-MHz
Bandwidth for Very Low Current Sensing
30.
An
On-Chip Monitoring Circuit for Signal-Integrity Analysis of 8-Gb/s Chip-to-Chip
Interfaces With Source-Synchronous Clock
31.
Resilience-Aware
Frequency Tuning for Neural-Network-Based Approximate Computing Chips
32.
Efficient
Soft Cancelation Decoder Architectures for Polar Codes
33.
Reconfigurable
Writing Architecture for Reliable RRAM Operation in Wide Temperature Ranges
34.
Low-Complexity
Transformed Encoder Architectures for Quasi-Cyclic Nonbinary LDPC Codes Over
Subfields
35.
A
0.13- μm CMOS Dynamically Reconfigurable Charge Pump for
Electrostatic MEMS Actuation
36.
A
Highly Efficient Ultralow Photovoltaic Power Harvesting System With MPPT for
Internet of Things Smart Nodes
37.
A
Flexible Continuous-Time ΔΣ ADC With Programmable Bandwidth Supporting Low-Pass and Complex
Bandpass Architectures
38.
Design
of Temperature-Aware Low-Voltage 8T SRAM in SOI Technology for High-Temperature
Operation (25 °C-300 °C)
39.
Multicast-Aware
High-Performance Wireless Network-on-Chip Architectures
40.
Logic-Base
Interconnect Design for Near Memory Computing in the Smart Memory Cube
41.
Seven-bit
700-MS/s Four-Way Time-Interleaved SAR ADC With Partial Vcm -Based Switching
42.
A
Programmable and Configurable Mixed-Mode FPAA SoC
43.
Design
of Defect and Fault-Tolerant Nonvolatile Spintronic Flip-Flops
44.
Near-Threshold
RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices
45.
Design
and Applications of Approximate Circuits by Gate-Level Pruning
46.
A
4096-Point Radix-4 Memory-Based FFT Using DSP Slices
47.
High-Frequency
CMOS Active Inductor: Design Methodology and Noise Analysis
--------------------------------------------------------------------------------------------------------------
