I2C Protocol implementation using VHDL - FPGA

Designing algorithms in VHDL

Algorithms

We always need to specify certain algorithm to run our system in a systematic way where it will not stuck up at some logic or uncleared routines.

Now a days it is vital to write source codes without having such bugs. VHDL provides efficient writing methodologies it follows behavioral programming idea.

Understand how the functional design works, make a algorithm steps, Write down the check out points where you can identify your internal signals

Write proper test Bench to test each modules and routines seperately

VHDL Code to generate a Simple Node based Algorithm is given below.
:Here i shown you how to create a simple network on Chip algorithm used to generate NODE of various conditions.

--Module to define the NODE FLOW

Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;



entity nodes_gb is
port (clk,clr: in std_logic;
e1,e2,e3,e4,e5 : out std_logic;
nodea,nodeb,nodec,nodee,noded: in std_logic_vector(7 downto 0));
end nodes_gb;

architecture behave of nodes_gb is
    signal en_nodea,en_nodeb,en_nodec,en_noded,en_nodee: std_logic;
    signal n1,n2,n3,n4,n5 : std_logic_vector(3 downto 0); -- NW FLOW
    signal r1,r2,r3,r4,r5 : string(1 to 6);
--signal  nodea,nodeb,nodec,nodee,noded:  std_logic_vector(7 downto 0)    ;
begin      

en_nodea<= (not nodea(3) ) and (not nodea(2) ) and (not nodea(1) ) and ( nodea(0) );
en_nodeb<= (not nodeb(3) ) and (not nodeb(2) ) and (not nodeb(1) ) and ( nodeb(0) );
en_nodec<= (not nodec(3) ) and (not nodec(2) ) and (not nodec(1) ) and ( nodec(0) );
en_noded<= (not noded(3) ) and (not noded(2) ) and (not noded(1) ) and ( noded(0) );
en_nodee<= (not nodee(3) ) and (not nodee(2) ) and (not nodee(1) ) and ( nodee(0) );
   

c2 : process(en_nodea,clr)
begin
    if clr='1' then
        n1<="0000"; 
        r1<="XXXXXX";     
elsif  rising_edge(en_nodea) then
        n1<="1010";  --A
        r1<="NODE-A";       
end if;
end process c2;         


c3 : process(en_nodeb,clr)
begin
    if clr='1' then
        n2<="0000";
        r2<="XXXXXX";                     
elsif  rising_edge(en_nodeb) then
        n2<="1011";  --B
        r2<="NODE-A";     
end if;
end process c3;         


c4 : process(en_nodec,clr)
begin
    if clr='1' then
        n3<="0000";
        r3<="XXXXXX";                                     
elsif  rising_edge(en_nodec) then
        n3<="1100"; -- c
        r3<="NODE-C";             
end if;
end process c4;         


c5 : process(en_noded,clr)
begin
    if clr='1' then
        n4<="0000"; 
        r4<="XXXXXX";                                                   
elsif  rising_edge(en_noded) then
        n4<="1010";  -- D
        r4<="NODE-D";                     
end if;
end process c5; 


c6 : process(en_nodee,clr)
begin
    if clr='1' then
        n5<="0000"; 
        r5<="XXXXXX";                                                                 
elsif  rising_edge(en_nodee) then
        n5<="1010";  -- E
        r5<="NODE-E";                             
end if;
end process c6;        

e1<=en_nodea;
e2<=en_nodeb;
e3<=en_nodec;
e4<=en_noded;
e5<=en_nodee;


end behave;

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VLDL code for predictive tuning circuit

Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.math_real.all;
use ieee.numeric_std.all;


ENTITY Predictive_control_single is
port(clk,clr: in std_logic;
pred_in : in real;
adc_resol: out real);
end Predictive_control_single;


architecture behave of Predictive_control_single is

signal sel : std_logic_vector(3 downto 0);


begin
   
mem_predictor:process(pred_in,clk,clr)
begin
if clr='1' then
    sel<="0000";
    elsif rising_edge(clk) then
       
       if (pred_in>0.00) and (pred_in<100.00) then 
             sel<="0001";
       end if;

if (pred_in>100.00) and (pred_in<125.00) then 
             sel<="0001";
       end if;

if (pred_in>125.00) and (pred_in<150.00) then 
             sel<="0010";
       end if;

if (pred_in>150.00) and (pred_in<175.00) then 
             sel<="0011";
       end if;

if (pred_in>175.00) and (pred_in<200.00) then 
             sel<="0100";
       end if;

if (pred_in>200.00) and (pred_in<225.00) then 
             sel<="0101";
       end if;

if (pred_in>225.00) and (pred_in<350.00) then 
             sel<="0110";
       end if;

if (pred_in>350.00) and (pred_in<475.00) then 
             sel<="0111";
       end if;

if (pred_in>475.00) and (pred_in<500.00) then 
             sel<="1000";
       end if;

if (pred_in>500.00) and (pred_in<725.00) then 
             sel<="1001";
       end if;

   if (pred_in>725.00) and (pred_in<850.00) then 
             sel<="1010";
       end if;   

if (pred_in>850.00) and (pred_in<975.00) then 
             sel<="1011";
       end if;

if (pred_in>975.00) and (pred_in<1200.00) then 
             sel<="1100";
       end if;
             
end if;       
end process mem_predictor;   
   

sel_range:process(sel)
begin
    if clr='1' then

adc_resol<= 0.000;
        else
        case sel is
            when "0001" => adc_resol <=0.500;

           
            when "0010" => adc_resol <=1.000;

                           
            when "0011" => adc_resol <= 1.500;


            when "0100" => adc_resol <= 2.000;

                          
            when "0101" => adc_resol <= 2.500;

                          
            when "0110" => adc_resol <= 3.000;

                          
            when "0111" => adc_resol <= 3.500;

                           
            when "1000" => adc_resol <= 4.000;

                           
            when "1001" => adc_resol <= 4.500;

                           
            when "1010" => adc_resol <= 5.000;


            when "1011" => adc_resol <= 5.500;

                           
            when "1100" => adc_resol <= 6.000;

          
              when others => adc_resol <= 0.000;

              end case;
          end if;         
                                                                  
end process sel_range;


 

end behave;   

vlsi implementation of FFT

Configurable FFT using mixed radix form

Module 1: Design of FFT Block

The FFT computation is accomplished in three stages. The x(0) until x(15) variables are denoted as the input values for FFT computation and X(0) until X(15) are denoted as the outputs. The pipeline architecture of the 16 point FFT is shown in Fig 4.1 consisting of butterfly schemes in it. There are two operations to complete the computation in each stage. Which is implemented in the FFT BLOCK.

Module 2: Design of Control unit

FFT Computation can be controlled using a software controlled finite state machine control algorithm written in VHDL.Reference signals are used to control the data flow and address flow.

Module 3: Design of adder & Subtractor section

This module consists of adder and subtractor sections used for calculating the fft co-efficients. Here in our project we have a single adder and using timing control the number of adder can be reduced.

Module 4: Design of Integration module

This module consists of integration of sub modules with respect to clock and other synchronization procedures are done over here.

ADC Design using Super advanced pulse code modulation Technique

Design of Super advanced PULSE CODE MODULATION based ADC converter is realized here

Modules includes:

• Design of Analog Signal Generator
• Deign of Sampling 
• Design of Quantizing
• Design of SAPCM coder
• Integration Module

LANGUAGE : VHDL

TOOLS : MODELSIM 6.3G ALTERA 

IMPLEMENTATION : XILINX 12.5

Simulation Result Below contact us for SOURE CODE & DOCUMENTATION

Design of DSP-Enhanced Analog-to-Digital Conversion for High-Speed Data Centers' Optical Connectivities IEEE project

Proposed BLOCK DIAGRAM

• FPGA act as a emulator here, we designed a FPGA Configurabl;e system for generating the input samples through digital PAM sampler and encoding schemes

• FPGA all the most act as a control device here, a complete adc system is realized here , the advanced PCM methodology is applied here for coding.

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A Low-Complexity Turbo Decoder Architecture for Energy-Efficient Wireless Sensor Networks

A Low-Complexity Turbo Decoder Architecture for

Energy-Efficient Wireless Sensor Networks

Abstract:-

Energy constrained wireless communication applications realization is done here, to facilitate low transmission energy consumption, reduce the overall energy consumption; lookup table-log-BCJR (LUT-Log-BCJR) architectures having low processing energy consumption are required. In this existing design, we decompose the LUT-Log-BCJR architecture into its most fundamental add compare select (ACS) operations and perform them using a novel low-complexity ACS unit. We demonstrate that our architecture employs an order of magnitude fewer gates than the most recent LUT-Log-BCJR architectures, facilitating a 71% energy consumption reduction. Compared to state-of-the-art maximum logarithmic Bahl-Cocke-Jelinek-Raviv implementations, our approach facilitates a 10% reduction in the overall energy consumption at ranges above 58 m.

Existing System:-                            

In this existing design, we implemented the LUT-Log-BCJR architecture into its most fundamental add compare select (ACS) operations and perform them using a novel low-complexity ACS unit. The demonstration also simulates the energy efficiency, and power reduction as shown in this paper.

Proposed System:-

In the proposed system the LUT log BCJR is designed with Clock gating technique which leads to reduction in Power consumption and energy consumption reduction is carried out. The circuit is converted into digital hardware.

Module Description

Module 1: Design of

 Software Requirements:-

Design Environment: XILINX ISE

Language: VHDL

Simulation: MODELSIM / XILINX ISE Simulator

Hardware Requirements’:-

XILINX SPARTAN Development Board

Device: XC3S500E       

Simple Source Code in VHDL for a Clock Divider

-- LIBRARY DECLARATION

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

-- ENTITY DECLARATION

Entity clkdiv is
port(clk,clr: in std_logic;
divided_clock: out std_logic);
end entity clkdiv;

architecture behave of clkdiv is
signal tclk: std_logic;
begin

Clock_divider_Block:process(clk,clr)
begin
if clr='1' then
     tclk <='0';
elsif rising_edge(clk) then
     tclk<= not tclk;
end if;
end process Clock_divider_Block;

-- output
divided_clock  <=  tclk;

end behave;

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