How to dump FPGA the RTL code

How to dump the RTL code into the FPGA

RTL codes are developed in VHDL (Very high speed integrated circuirs - Hardware description language) or Verilog HDL.

The logical designs are realized using the Logical gates through combinational and sequential logics.

The circuits are converted into hardware understandable code

The converted codes are synthesized using XILINX ISE or any other integrated software environment and dumped into the FPGA through Hardware emulator

The important pins for making the programming or the dumping part is the TCK, TDI,TDO, TMS 

TCK is the test clock, TDI is the Test data input, TDO is the Test data output and TMS are the Test mode select provided in the XILINX emulator

The emulator and the JTAG from fpga kit is configured one to one mechanism

usign Boundary scan the cable connectivities are tested and dumping process takes place.

the Dump file should be .JED 

Further the testing of hardware is evaluated through Digital oscilloscopes.

DM for more details.

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