Design of FIR FILTER with Configurable LUT using 4:2 Compressor and 7:2 Compressor
FIR filters are applications which require many multiply-and-accumulate operations which consume more space. The good digital design consists of reduced multipliers, to reduce the FPGA Accumulation cost.To achieve this kind of circuits we need to create circuits with reduced multipliers or multiplierless Distribute arithmetic concepts.
The Distributed arithmetic FIR filter can be classified as two types: the first type stores the coefficients in look-up tables (LUTs).the second part adds the outputs of these LUTs and calculates the final FIR filter output using an adder tree.
These kind of filters have a very compact structure and can be efficiently mapped to LUT-based FPGAs, . Furthermore, DA method is very much suitable for reconfigurable designs, where the coefficients are available to be changed during run time.
Despite the fact that the storage space grows increasingly with filter taps, this issue can be solved by replacing a large LUT with several small LUTs Few research analyzed the optimal input bit width of these small LUTs on Xilinx FPGAs and proved that a better implementation can be achieved when the input bit width is close to the number of LUT inputs in FPGAs
The proposed method comprises of 4:2 Compression and 7:2 Compression using reconfigurable LUTS where the FIR Coefficients can be varied at run time.The design can be extended further too depends upon the required application.
Simulation Results
VIDEO OUTPUT
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