Monday 25 December 2017

Medical image processing using FPGA


Medical image processing using FPGA

Medical images are more complicated one with minute points contains info of the particular diagnostic issues.Processing such medical images need more accurate algorithm which will synchronize with the machine frequency and measuring device frequency.

Capturing the medical images are done by MRI scan and CT Scan.VLSI design plays a good role in processing the image values efficiently.VLSI projects related to medical imaging involves in iterative classifications and unique algorithms to improve the accuracy.

MRI CT scanned images are feature extracted and image features are studied.Color pixel values are further converted into gray scale images.Image size is being resized for  matching with the processing matrix.The resized image values are further dilated and edge detected.

The final threshold values are processed using FPGA Hardware where the improved DCT algorithm is developed.Discrete cosine transform is being implemented in the Digital environment in which the frequency of operation is variable and the digital blocks are configurable.

IO ports are connected with wireless transceivers to enable the information send and receive can be done in a easy and quick way.Now a days IOT plays a major role.To send and view the processed info in IOT screen globally the resultant values are sent to a cloud to display in the IOT Window.

BLOCK DIAGRAM






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Friday 15 December 2017

IEEE project on VLSI Design Converting RF to SERDES for a Configurable communication system

  RF to Serializer and Deserializer

Increasing demands in mobile technology are pushing cellular network capacity.Henceforth Massive MIMO antenna with larger data communicating base stations are become more wider on the way.

The advancements in CMOS Technology and Configurable design enable the engineers doing various inventions in VLSI platforms which gives solution to realtime RF Communications.

There also challenges in integrating complex algorithms in a single SOC which create route for large interference and chip level power issues.leakage current and voltages.RF to serializer and deserializer is one of the technique used to enable the use of input signals easier.

Such a circuit process the large data sets from MASSIVE MIMO to enable the communication speed processing time linear.  Configurable platforms always ensure the flexible architecture where one can include future requirements too. One kind of RF to SERDES is designed here. Output video is simulated here.

Inputs area RF in nature which are given to a LNA , filter section , and analog to digital converter, the same vice versa in Serdes to RF. SERDES is nothing but serializer and Deserializer.

These convert the continuous wave analog signal and process the modulation works and serialize to the required speed.



Block Diagram

  Simulation Screen shots







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