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DESIGN & IMPLEMENTATION OF POWER SAVING SYNTHESIZER

Introduction

o    Design of Low power energy saving digital circuit is realized here

o    Design of Frequency synthesizer designed as a application is established using low power logics

o    The architecture is designed in such a way the power dissipation can be avoided during static mode as well as dynamic mode

Existing System

•         In the existing system, Multiplexer is designed

•         Leakage of power is analyzed

•         Power leakage due to capacitance is analyzed

Proposed System

•        In the proposed system design of application module Frequency synthesizer is realized here

•        Design architecture is design with Low power circuits to reduce power

•        The proposed design also contains leakage avoidance circuits to save resource

Literature Survey

Title

Statistical Analysis and Optimization for Timing and Power of VLSI

Author

By L Cheng – 2010

Analysis On: Deterministic Device and Architecture Co-

Optimization for FPGA Power,. Delay, and Area

Minimization., tells that the gate delay as linear functions of variation sources and assumed all the variation sources are by leakage sources

Title

Reduction of Power Consumption in FPGAs

Author

N Grover - 2012 Analysis on :

Low power digital modules to reduce the power dissipation and review the work carried out in this area and The programming technology for the logic and interconnect resources can be.

Problem Formulation

•         Leakage power due to transient effect in transistor switching

•         Leakage of power due to unused logics and area utilized by the same

Objective

•         To design a low power architecture for Frequency synthesizer using Low power techniques

•         To design a unused power wastage avoidance circuit to utilize the power efficiently

Design Block diagram

Advantages

•         High speed design with power saving modules

•         Low power circuits with area efficient architecture

•         Reliable code and code reusability

Applications

•       High speed modems

•       Real time wireless networks

•       Communication systems

•       Medical equipments

Truncated Multiplier VHDL code and results

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CODE

Library ieee;
use ieee.std_logic_1164.all;

entity trunc_mul is
port(
a,b: in std_logic_vector(7 downto 0);
pout:out std_logic_vector(7 downto 0));
end entity trunc_mul;

architecture behave of trunc_mul is

COMPONENT fa is
port(p,q,r: in std_logic;
     sum,carry: out std_logic);
end COMPONENT;

COMPONENT multiplicants is
port(a,b: in std_logic_vector(7 downto 0);
m1,m2,m3,m4,m5,m6,m7,m8,m9,m10: out std_logic;
m11,m12,m13,m14,m15,m16,m17,m18,m19,m20: out std_logic;
m21,m22,m23,m24,m25,m26,m27,m28,m29,m30: out std_logic;
m31,m32,m33,m34,m35,m36,m37,m38,m39,m40,m41,m42,m43: out std_logic);
end COMPONENT;

signal n1,n2,n3,n4,n5,n6,n7,n8,n9,n10,n11,n12,n13,n14,n15,n16,n17,n18,n19,n20,n21,n22,n23,n24,n25,n26,n27,n28,n29,n30,n31,n32,n33,n34,n35,n36,n37,n38,n39,n40,n41,n42,n43 : std_logic;


signal s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15,s16,s17,s18,s19,s20,s21,s22,s23,s24,s25,s26,s27,s28: std_logic;

signal c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,c13,c14,c15,c16,c17,c18,c19,c20,c21,c22,c23,c24,c25,c26,c27,c28: std_logic;

signal k: std_logic;
signal c8a,c9a,c10a,c11a,c12a,c13a: std_logic;



begin
   
mul:multiplicants port map(a,b,n1,n2,n3,n4,n5,n6,n7,n8,n9,n10,n11,n12,n13,
n14,n15,n16,n17,n18,n19,n20,n21,n22,n23,n24,n25,n26,n27,n28,n29,n30,
n31,n32,n33,n34,n35,n36,n37,n38,n39,n40,n41,n42,n43);   
   
fa1: fa port map(n1,n2,n3,s1,c1); 
fa2: fa port map(s1,n4,n5,s2,c2);
fa3: fa port map(s2,n6,n7,s3,c3);
fa4: fa port map(s3,n8,n9,s4,c4);
fa5: fa port map(s4,n10,n11,s5,c5);
fa6: fa port map(s5,n12,n13,s6,c6); 
fa7: fa port map(n6,n14,n15,s7,c7);



fa9: fa port map(n17,n18,c1,s8,c8);
fa10: fa port map(s8,n19,c2,s9,c9);
fa11: fa port map(s9,n20,c3,s10,c10); 
fa12: fa port map(s10,n21,c4,s11,c11);
fa13: fa port map(s11,n22,c5,s12,c12);
fa14: fa port map(s12,n23,c6,s13,c13);


fa16: fa port map(n24,n25,c8,s14,c14); 
fa17: fa port map(s14,n26,c9,s15,c15);
fa18: fa port map(s15,n27,c10,s16,c16);
fa19: fa port map(s16,n28,c11,s17,c17);
fa20: fa port map(s17,n29,c12,s18,c18);



fa22: fa port map(n30,n31,c14,s19,c19);
fa23: fa port map(s19,n32,c15,s20,c20);
fa24: fa port map(s20,n33,c16,s21,c21);
fa25: fa port map(s21,n34,c17,s22,c22);


 
fa27: fa port map(n35,n36,c19,s23,c23);
fa28: fa port map(s23,n37,c20,s24,c24);
fa29: fa port map(s24,n38,c21,s25,c25);


fa31: fa port map(n39,n40,c23,s26,c26); 
fa32: fa port map(s26,n41,c24,s27,c27);


fa34: fa port map(n42,n43,c26,s28,c28);

--********************************************************

fa8: fa port map(n16,s7,c13a,p14,p15);
fa15: fa port map(c7,s13,c12a,p13,c13a);
fa21: fa port map(c13,s18,c11a,p12,c12a);
fa26: fa port map(c18,s22,c10a,p11,c11a);
fa30: fa port map(c22,s25,c9a,p10,c10a);
fa33: fa port map(c25,s27,c8a,p9,c9a);
fa35: fa port map(c27,s28,k,p8,c8a);
--------------------------------------------------------------------- 
k<='1';

pout(0)<=p8;
pout(1)<=p9;
pout(2)<=p10;
pout(3)<=p11;
pout(4)<=p12;
pout(5)<=p13;
pout(6)<=p14;
pout(7)<=p15;

signal p8,p9,p10,p11,p12,p13,p14,p15
end behave;   

RESULTS

 

 

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PHD Project Low-Power FPGA controlled ECG-acquisition System for detection of Cardiac Diseases

 

Module Description

Design of ECG data read Module

ü  In the proposed Design Multiple data sets can be extracted from different patients who is having cardiac disease and who appears normal in cardiac system can be takes as test.

ü  The data sets are nothing but the patient’s original electro-cardio gram peak voltage values taken as PQRST waves

ü  These data are further stored in a text file for file reading

ü  In the VHDL code we write a file read process which read the peak voltage values in decimal or binary format. Which is converted in a simple MATLAB code

Design of Signal analysis Module

ü  The information are further stored in a dedicated digital LUT designed in VHDL code.

ü  Signal Analysis Module is used to classify the signal information peak values and pick the best value to process.

ü  ECG information have lots of peak threshold levels, each levels conveys the disease related accurate check points

ü  We have a detailed data base of cardiac disease which are able to detect by the PQRST wave can be stored in separate Latched Flip flop based LUTS

ü  Example, If a patient is possibly have a mild attach his PQRST check points such as ELOW will be less threshold , NR enabled will be HIGH in state.These kind of threshold information are stored in a clock controlled LATCHES

Design of Classification Algorithm

ü  In the Classification Module we get the constant values of check points which are going to be considered.

ü  Input patient samples are also further multiplied with a fixed constant to make the measurement more accurate.

Design of integration module

ü  Integration module consists of port mapping algorithm, component declarations to enable the main module enclose the sub modules with the Top module.

ü  The architecture of the proposed was able to work with min of KHZ to High speed of MHZ for storing.

ü  Data are predicted with respect to the heart pulses. Various cardiac diseases can be detected by this method efficiently.

Advantages of Proposed Design

ü  Data acquisition accuracy is increased to 90%

ü  Multiple cardiac diseases can be detected

ü  Critical Points are measured in high resolution

 

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matlab projects in kodambakkam : Brain tumor detection

Brain Tumor Detection and simulation using MATLAB

This project consist of image processing techniques such as image segmentation, image feature extraction, resolution and edge detection etc

This project get the input sample image of the affected person through MRI scan or CT scan. The captured image is further converted into binary values using matlab command

The binary values are nothing but the Black and white pixel information of the image which is took from the person having disease. The info are stored in a single array for processing

The image info is further processed in matlab for segmentation process and feature extraction process. various image processing algorithms are available in MATLAB core area, in IEEE project implementation the image processing tool box is highly helpful

Depends upon the final year students requirement the algorithm can be changed and finaly by applying the specific algorithm , the image is being compared with various threshold levels and resultant image value is displayed in which the tumor affected area is detected.

Simulation result is shown below:

Contact us for more info &Source Code 
http://vlsiprojectss.blogspot.in/p/contact-us.html 

 
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ieee projects centre in chennai: sample vhdl code FFT 64Points

64 Point FFT VHDL Code

library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
use work.fft_package.all;

entity fft64 is
    port    (    clk    :    in std_logic;       
            reset    :    in std_logic;
            start    :    in std_logic;

            in_re:    in real;            --get inputs in serial manner           
            in_im:    in real;

            out_re:    out real;            --get output in serial manner
            out_im:    out real;

            done    :    out std_logic
        );
end;

architecture rtl of fft64 is

type memory is array(0 to 63) of real;
signal in_reg_re:memory;
signal in_reg_im:memory;
signal out_reg_re:memory;
signal out_reg_im:memory;


signal cnt,rcnt:integer:=0;
signal load,tdone,tstart1,tstart:std_logic;
signal s1_re,s1_im:real;
signal s2_re,s2_im:real;
signal s3_re,s3_im:real;
signal s4_re,s4_im:real;
signal s5_re,s5_im:real;
signal s6_re,s6_im:real;
signal s7_re,s7_im:real;

signal s8_re,s8_im:real;
signal s9_re,s9_im:real;
signal s10_re,s10_im:real;
signal s11_re,s11_im:real;
signal s12_re,s12_im:real;
signal s13_re,s13_im:real;
signal s14_re,s14_im:real;
signal s15_re,s15_im:real;

signal s16_re,s16_im:real;
signal s17_re,s17_im:real;
signal s18_re,s18_im:real;
signal s19_re,s19_im:real;
signal s20_re,s20_im:real;
signal s21_re,s21_im:real;
signal s22_re,s22_im:real;
signal s23_re,s23_im:real;
signal s24_re,s24_im:real;
signal s25_re,s25_im:real;
signal s26_re,s26_im:real;
signal s27_re,s27_im:real;
signal s28_re,s28_im:real;
signal s29_re,s29_im:real;
signal s30_re,s30_im:real;
signal s31_re,s31_im:real;


signal w0_re,w0_im:real;
signal w1_re,w1_im:real;

begin

--testing
W0_re<=w_re(0.0);
w0_im<=w_im(0.0);

W1_re<=w_re(1.0);
w1_im<=w_im(1.0);

    process(clk,reset)
    begin
        if reset='1' then
            out_re<=0.0;
            out_im<=0.0;
            in_reg_re<=(others=>0.0);
            in_reg_im<=(others=>0.0);

            out_reg_re<=(others=>0.0);
            out_reg_im<=(others=>0.0);

            cnt<=0;
            load<='0';
            done<='0';
            tdone<='0';
            tstart1<='0';
            tstart<='0';
           
            s1_re<=0.0;s1_im<=0.0;
            s2_re<=0.0;s2_im<=0.0;
            s3_re<=0.0;s3_im<=0.0;
            s4_re<=0.0;s4_im<=0.0;
            s5_re<=0.0;s5_im<=0.0;
            s6_re<=0.0;s6_im<=0.0;
            s7_re<=0.0;s7_im<=0.0;               
            s8_re<=0.0;s8_im<=0.0;
            s9_re<=0.0;s9_im<=0.0;
            s10_re<=0.0;s10_im<=0.0;
            s11_re<=0.0;s11_im<=0.0;
            s12_re<=0.0;s12_im<=0.0;
            s13_re<=0.0;s13_im<=0.0;
            s14_re<=0.0;s14_im<=0.0;   
            s15_re<=0.0;s15_im<=0.0;   

            s16_re<=0.0;s16_im<=0.0;
            s17_re<=0.0;s17_im<=0.0;
            s18_re<=0.0;s18_im<=0.0;
            s19_re<=0.0;s19_im<=0.0;
            s20_re<=0.0;s20_im<=0.0;
            s21_re<=0.0;s21_im<=0.0;
            s22_re<=0.0;s22_im<=0.0;               
            s23_re<=0.0;s23_im<=0.0;
            s24_re<=0.0;s24_im<=0.0;
            s25_re<=0.0;s25_im<=0.0;
            s26_re<=0.0;s26_im<=0.0;
            s27_re<=0.0;s27_im<=0.0;
            s28_re<=0.0;s28_im<=0.0;
            s29_re<=0.0;s29_im<=0.0;   
            s30_re<=0.0;s30_im<=0.0;
            s31_re<=0.0;s31_im<=0.0;
           
        elsif clk'event and clk='1' then

            tstart1<=start;
            tstart<=tstart1;
                       
            if tstart1='1' then
                if cnt<=63 then
                    cnt<=cnt+1;
                    in_reg_re(cnt)<=in_re;
                    in_reg_im(cnt)<=in_im;
                else
                    load<='1'; --data loaded
                end if;--cnt

                if load='1' then
                   
                    out_reg_re(0)<=in_reg_re(0)+in_reg_re(32);
                    out_reg_im(0)<=in_reg_im(0)+in_reg_im(32);
                   
                    out_reg_re(1)<=in_reg_re(1)+in_reg_re(33);
                    out_reg_im(1)<=in_reg_im(1)+in_reg_im(33);
                   
                    out_reg_re(2)<=in_reg_re(2)+in_reg_re(34);
                    out_reg_im(2)<=in_reg_im(2)+in_reg_im(34);

                    out_reg_re(3)<=in_reg_re(3)+in_reg_re(35);
                    out_reg_im(3)<=in_reg_im(3)+in_reg_im(35);
                   
                    out_reg_re(4)<=in_reg_re(4)+in_reg_re(36);
                    out_reg_im(4)<=in_reg_im(4)+in_reg_im(36);
                   
                    out_reg_re(5)<=in_reg_re(5)+in_reg_re(37);
                    out_reg_im(5)<=in_reg_im(5)+in_reg_im(37);
                   
                    out_reg_re(6)<=in_reg_re(6)+in_reg_re(38);
                    out_reg_im(6)<=in_reg_im(6)+in_reg_im(38);

                    out_reg_re(7)<=in_reg_re(7)+in_reg_re(39);
                    out_reg_im(7)<=in_reg_im(7)+in_reg_im(39);

                    out_reg_re(8)<=in_reg_re(8)+in_reg_re(40);
                    out_reg_im(8)<=in_reg_im(8)+in_reg_im(40);
                   
                    out_reg_re(9)<=in_reg_re(9)+in_reg_re(41);
                    out_reg_im(9)<=in_reg_im(9)+in_reg_im(41);
                   
                    out_reg_re(10)<=in_reg_re(10)+in_reg_re(42);
                    out_reg_im(10)<=in_reg_im(10)+in_reg_im(42);
                   
                    out_reg_re(11)<=in_reg_re(11)+in_reg_re(43);
                    out_reg_im(11)<=in_reg_im(11)+in_reg_im(43);
                   
                    out_reg_re(12)<=in_reg_re(12)+in_reg_re(44);
                    out_reg_im(12)<=in_reg_im(12)+in_reg_im(44);
                   
                    out_reg_re(13)<=in_reg_re(13)+in_reg_re(45);
                    out_reg_im(13)<=in_reg_im(13)+in_reg_im(45);
                   
                    out_reg_re(14)<=in_reg_re(14)+in_reg_re(46);
                    out_reg_im(14)<=in_reg_im(14)+in_reg_im(46);
                   
                    out_reg_re(15)<=in_reg_re(15)+in_reg_re(47);
                    out_reg_im(15)<=in_reg_im(15)+in_reg_im(47);
                   
                    out_reg_re(16)<=in_reg_re(16)+in_reg_re(48);
                    out_reg_im(16)<=in_reg_im(16)+in_reg_im(48);

                    out_reg_re(17)<=in_reg_re(17)+in_reg_re(49);
                    out_reg_im(17)<=in_reg_im(17)+in_reg_im(49);

                    out_reg_re(18)<=in_reg_re(18)+in_reg_re(50);
                    out_reg_im(18)<=in_reg_im(18)+in_reg_im(50);

                    out_reg_re(19)<=in_reg_re(19)+in_reg_re(51);
                    out_reg_im(19)<=in_reg_im(19)+in_reg_im(51);

                    out_reg_re(20)<=in_reg_re(20)+in_reg_re(52);
                    out_reg_im(20)<=in_reg_im(20)+in_reg_im(52);

                    out_reg_re(21)<=in_reg_re(21)+in_reg_re(53);
                    out_reg_im(21)<=in_reg_im(21)+in_reg_im(53);

                    out_reg_re(22)<=in_reg_re(22)+in_reg_re(54);
                    out_reg_im(22)<=in_reg_im(22)+in_reg_im(54);

                    out_reg_re(23)<=in_reg_re(23)+in_reg_re(55);
                    out_reg_im(23)<=in_reg_im(23)+in_reg_im(55);

                    out_reg_re(24)<=in_reg_re(24)+in_reg_re(56);
                    out_reg_im(24)<=in_reg_im(24)+in_reg_im(56);

                    out_reg_re(25)<=in_reg_re(25)+in_reg_re(57);
                    out_reg_im(25)<=in_reg_im(25)+in_reg_im(57);

                    out_reg_re(26)<=in_reg_re(26)+in_reg_re(58);
                    out_reg_im(26)<=in_reg_im(26)+in_reg_im(58);

                    out_reg_re(27)<=in_reg_re(27)+in_reg_re(59);
                    out_reg_im(27)<=in_reg_im(27)+in_reg_im(59);

                    out_reg_re(28)<=in_reg_re(28)+in_reg_re(60);
                    out_reg_im(28)<=in_reg_im(28)+in_reg_im(60);

                    out_reg_re(29)<=in_reg_re(29)+in_reg_re(61);
                    out_reg_im(29)<=in_reg_im(29)+in_reg_im(61);

                    out_reg_re(30)<=in_reg_re(30)+in_reg_re(62);
                    out_reg_im(30)<=in_reg_im(30)+in_reg_im(62);

                    out_reg_re(31)<=in_reg_re(31)+in_reg_re(63);
                    out_reg_im(31)<=in_reg_im(31)+in_reg_im(63);

                    -------------------------------------------
                   
                    out_reg_re(32)<=in_reg_re(0)-in_reg_re(32);
                    out_reg_im(32)<=in_reg_im(0)-in_reg_im(32);

                    s1_re<=in_reg_re(1)-in_reg_re(33);
                    s1_im<=in_reg_im(1)-in_reg_im(33);

                    out_reg_re(33)<=c_mult_re(s1_re,s1_im,w_re(1.0),w_im(1.0));
                    out_reg_im(33)<=c_mult_im(s1_re,s1_im,w_re(1.0),w_im(1.0));

                    s2_re<=in_reg_re(2)-in_reg_re(34);
                    s2_im<=in_reg_im(2)-in_reg_im(34);

                    out_reg_re(34)<=c_mult_re(s2_re,s2_im,w_re(2.0),w_im(2.0));
                    out_reg_im(34)<=c_mult_im(s2_re,s2_im,w_re(2.0),w_im(2.0));

                    s3_re<=in_reg_re(3)-in_reg_re(35);
                    s3_im<=in_reg_im(3)-in_reg_im(35);

                    out_reg_re(35)<=c_mult_re(s3_re,s3_im,w_re(3.0),w_im(3.0));
                    out_reg_im(35)<=c_mult_im(s3_re,s3_im,w_re(3.0),w_im(3.0));

                    s4_re<=in_reg_re(4)-in_reg_re(36);
                    s4_im<=in_reg_im(4)-in_reg_im(36);

                    out_reg_re(36)<=c_mult_re(s4_re,s4_im,w_re(4.0),w_im(4.0));
                    out_reg_im(36)<=c_mult_im(s4_re,s4_im,w_re(4.0),w_im(4.0));
                   
                    s5_re<=in_reg_re(5)-in_reg_re(37);
                    s5_im<=in_reg_im(5)-in_reg_im(37);

                    out_reg_re(37)<=c_mult_re(s5_re,s5_im,w_re(5.0),w_im(5.0));
                    out_reg_im(37)<=c_mult_im(s5_re,s5_im,w_re(5.0),w_im(5.0));
                   
                    s6_re<=in_reg_re(6)-in_reg_re(38);
                    s6_im<=in_reg_im(6)-in_reg_im(38);

                    out_reg_re(38)<=c_mult_re(s6_re,s6_im,w_re(6.0),w_im(6.0));
                    out_reg_im(38)<=c_mult_im(s6_re,s6_im,w_re(6.0),w_im(6.0));
                   
                    s7_re<=in_reg_re(7)-in_reg_re(39);
                    s7_im<=in_reg_im(7)-in_reg_im(39);

                    out_reg_re(39)<=c_mult_re(s7_re,s7_im,w_re(7.0),w_im(7.0));
                    out_reg_im(39)<=c_mult_im(s7_re,s7_im,w_re(7.0),w_im(7.0));
                   
                    s8_re<=in_reg_re(8)-in_reg_re(40);
                    s8_im<=in_reg_im(8)-in_reg_im(40);

                    out_reg_re(40)<=c_mult_re(s8_re,s8_im,w_re(8.0),w_im(8.0));
                    out_reg_im(40)<=c_mult_im(s8_re,s8_im,w_re(8.0),w_im(8.0));
                   
                    s9_re<=in_reg_re(9)-in_reg_re(41);
                    s9_im<=in_reg_im(9)-in_reg_im(41);

                    out_reg_re(41)<=c_mult_re(s9_re,s9_im,w_re(9.0),w_im(9.0));
                    out_reg_im(41)<=c_mult_im(s9_re,s9_im,w_re(9.0),w_im(9.0));
                   
                    s10_re<=in_reg_re(10)-in_reg_re(42);
                    s10_im<=in_reg_im(10)-in_reg_im(42);

                    out_reg_re(42)<=c_mult_re(s10_re,s10_im,w_re(10.0),w_im(10.0));
                    out_reg_im(42)<=c_mult_im(s10_re,s10_im,w_re(10.0),w_im(10.0));
                   
                    s11_re<=in_reg_re(11)-in_reg_re(43);
                    s11_im<=in_reg_im(11)-in_reg_im(43);

                    out_reg_re(43)<=c_mult_re(s11_re,s11_im,w_re(11.0),w_im(11.0));
                    out_reg_im(43)<=c_mult_im(s11_re,s11_im,w_re(11.0),w_im(11.0));
                   
                    s12_re<=in_reg_re(12)-in_reg_re(44);
                    s12_im<=in_reg_im(12)-in_reg_im(44);

                    out_reg_re(44)<=c_mult_re(s12_re,s12_im,w_re(12.0),w_im(12.0));
                    out_reg_im(44)<=c_mult_im(s12_re,s12_im,w_re(12.0),w_im(12.0));
                   
                    s13_re<=in_reg_re(13)-in_reg_re(45);
                    s13_im<=in_reg_im(13)-in_reg_im(45);

                    out_reg_re(45)<=c_mult_re(s13_re,s13_im,w_re(13.0),w_im(13.0));
                    out_reg_im(45)<=c_mult_im(s13_re,s13_im,w_re(13.0),w_im(13.0));
                   
                    s14_re<=in_reg_re(14)-in_reg_re(46);
                    s14_im<=in_reg_im(14)-in_reg_im(46);

                    out_reg_re(46)<=c_mult_re(s14_re,s14_im,w_re(14.0),w_im(14.0));
                    out_reg_im(46)<=c_mult_im(s14_re,s14_im,w_re(14.0),w_im(14.0));
                   
                    s15_re<=in_reg_re(15)-in_reg_re(47);
                    s15_im<=in_reg_im(15)-in_reg_im(47);

                    out_reg_re(47)<=c_mult_re(s15_re,s15_im,w_re(15.0),w_im(15.0));
                    out_reg_im(47)<=c_mult_im(s15_re,s15_im,w_re(15.0),w_im(15.0));

                    s16_re<=in_reg_re(16)-in_reg_re(48);
                    s16_im<=in_reg_im(16)-in_reg_im(48);

                    out_reg_re(48)<=c_mult_re(s16_re,s16_im,w_re(16.0),w_im(16.0));
                    out_reg_im(48)<=c_mult_im(s16_re,s16_im,w_re(16.0),w_im(16.0));

                    s17_re<=in_reg_re(17)-in_reg_re(49);
                    s17_im<=in_reg_im(17)-in_reg_im(49);

                    out_reg_re(49)<=c_mult_re(s17_re,s17_im,w_re(17.0),w_im(17.0));
                    out_reg_im(49)<=c_mult_im(s17_re,s17_im,w_re(17.0),w_im(17.0));

                    s18_re<=in_reg_re(18)-in_reg_re(50);
                    s18_im<=in_reg_im(18)-in_reg_im(50);

                    out_reg_re(50)<=c_mult_re(s18_re,s18_im,w_re(18.0),w_im(18.0));
                    out_reg_im(50)<=c_mult_im(s18_re,s18_im,w_re(18.0),w_im(18.0));

                    s19_re<=in_reg_re(19)-in_reg_re(51);
                    s19_im<=in_reg_im(19)-in_reg_im(51);

                    out_reg_re(51)<=c_mult_re(s19_re,s19_im,w_re(19.0),w_im(19.0));
                    out_reg_im(51)<=c_mult_im(s19_re,s19_im,w_re(19.0),w_im(19.0));

                    s20_re<=in_reg_re(20)-in_reg_re(52);
                    s20_im<=in_reg_im(20)-in_reg_im(52);

                    out_reg_re(52)<=c_mult_re(s20_re,s20_im,w_re(20.0),w_im(20.0));
                    out_reg_im(52)<=c_mult_im(s20_re,s20_im,w_re(20.0),w_im(20.0));

                    s21_re<=in_reg_re(21)-in_reg_re(53);
                    s21_im<=in_reg_im(21)-in_reg_im(53);

                    out_reg_re(53)<=c_mult_re(s21_re,s21_im,w_re(21.0),w_im(21.0));
                    out_reg_im(53)<=c_mult_im(s21_re,s21_im,w_re(21.0),w_im(21.0));

                    s22_re<=in_reg_re(22)-in_reg_re(54);
                    s22_im<=in_reg_im(22)-in_reg_im(54);

                    out_reg_re(54)<=c_mult_re(s22_re,s22_im,w_re(22.0),w_im(22.0));
                    out_reg_im(54)<=c_mult_im(s22_re,s22_im,w_re(22.0),w_im(22.0));

                    s23_re<=in_reg_re(23)-in_reg_re(55);
                    s23_im<=in_reg_im(23)-in_reg_im(55);

                    out_reg_re(55)<=c_mult_re(s23_re,s23_im,w_re(23.0),w_im(23.0));
                    out_reg_im(55)<=c_mult_im(s23_re,s23_im,w_re(23.0),w_im(23.0));

                    s24_re<=in_reg_re(24)-in_reg_re(56);
                    s24_im<=in_reg_im(24)-in_reg_im(56);

                    out_reg_re(56)<=c_mult_re(s24_re,s24_im,w_re(24.0),w_im(24.0));
                    out_reg_im(56)<=c_mult_im(s24_re,s24_im,w_re(24.0),w_im(24.0));


                    s25_re<=in_reg_re(25)-in_reg_re(57);
                    s25_im<=in_reg_im(25)-in_reg_im(57);

                    out_reg_re(57)<=c_mult_re(s25_re,s25_im,w_re(25.0),w_im(25.0));
                    out_reg_im(57)<=c_mult_im(s25_re,s25_im,w_re(25.0),w_im(25.0));

                    s26_re<=in_reg_re(26)-in_reg_re(58);
                    s26_im<=in_reg_im(26)-in_reg_im(58);

                    out_reg_re(58)<=c_mult_re(s26_re,s26_im,w_re(26.0),w_im(26.0));
                    out_reg_im(58)<=c_mult_im(s26_re,s26_im,w_re(26.0),w_im(26.0));

                    s27_re<=in_reg_re(27)-in_reg_re(59);
                    s27_im<=in_reg_im(27)-in_reg_im(59);

                    out_reg_re(59)<=c_mult_re(s27_re,s27_im,w_re(27.0),w_im(27.0));
                    out_reg_im(59)<=c_mult_im(s27_re,s27_im,w_re(27.0),w_im(27.0));

                    s28_re<=in_reg_re(28)-in_reg_re(60);
                    s28_im<=in_reg_im(28)-in_reg_im(60);

                    out_reg_re(60)<=c_mult_re(s28_re,s28_im,w_re(28.0),w_im(28.0));
                    out_reg_im(60)<=c_mult_im(s28_re,s28_im,w_re(28.0),w_im(28.0));

                    s29_re<=in_reg_re(29)-in_reg_re(61);
                    s29_im<=in_reg_im(29)-in_reg_im(61);

                    out_reg_re(61)<=c_mult_re(s29_re,s29_im,w_re(29.0),w_im(29.0));
                    out_reg_im(61)<=c_mult_im(s29_re,s29_im,w_re(29.0),w_im(29.0));

                    s30_re<=in_reg_re(30)-in_reg_re(62);
                    s30_im<=in_reg_im(30)-in_reg_im(62);

                    out_reg_re(62)<=c_mult_re(s30_re,s30_im,w_re(30.0),w_im(30.0));
                    out_reg_im(62)<=c_mult_im(s30_re,s30_im,w_re(30.0),w_im(30.0));

                    s31_re<=in_reg_re(31)-in_reg_re(63);
                    s31_im<=in_reg_im(31)-in_reg_im(63);

                    out_reg_re(63)<=c_mult_re(s31_re,s31_im,w_re(31.0),w_im(31.0));
                    out_reg_im(63)<=c_mult_im(s31_re,s31_im,w_re(31.0),w_im(31.0));

                   
                    tdone<='1';

                end if;--load
                           
                if tdone='1' then
                    if rcnt<=63 then
                        out_re<=out_reg_re(rcnt);
                        out_im<=out_reg_im(rcnt);
                        rcnt<=rcnt+1;
                        done<='1';
                    end if;
                end if;
        end if;--start           
        end if;--reset
    end process;

end;