Algorithms
We always need to specify certain algorithm to run our system in a systematic way where it will not stuck up at some logic or uncleared routines.
Now a days it is vital to write source codes without having such bugs. VHDL provides efficient writing methodologies it follows behavioral programming idea.
Understand how the functional design works, make a algorithm steps, Write down the check out points where you can identify your internal signals
Write proper test Bench to test each modules and routines seperately
VHDL Code to generate a Simple Node based Algorithm is given below.
:Here i shown you how to create a simple network on Chip algorithm used to generate NODE of various conditions.
--Module to define the NODE FLOW
Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity nodes_gb is
port (clk,clr: in std_logic;
e1,e2,e3,e4,e5 : out std_logic;
nodea,nodeb,nodec,nodee,noded: in std_logic_vector(7 downto 0));
end nodes_gb;
architecture behave of nodes_gb is
signal en_nodea,en_nodeb,en_nodec,en_noded,en_nodee: std_logic;
signal n1,n2,n3,n4,n5 : std_logic_vector(3 downto 0); -- NW FLOW
signal r1,r2,r3,r4,r5 : string(1 to 6);
--signal nodea,nodeb,nodec,nodee,noded: std_logic_vector(7 downto 0) ;
begin
en_nodea<= (not nodea(3) ) and (not nodea(2) ) and (not nodea(1) ) and ( nodea(0) );
en_nodeb<= (not nodeb(3) ) and (not nodeb(2) ) and (not nodeb(1) ) and ( nodeb(0) );
en_nodec<= (not nodec(3) ) and (not nodec(2) ) and (not nodec(1) ) and ( nodec(0) );
en_noded<= (not noded(3) ) and (not noded(2) ) and (not noded(1) ) and ( noded(0) );
en_nodee<= (not nodee(3) ) and (not nodee(2) ) and (not nodee(1) ) and ( nodee(0) );
c2 : process(en_nodea,clr)
begin
if clr='1' then
n1<="0000";
r1<="XXXXXX";
elsif rising_edge(en_nodea) then
n1<="1010"; --A
r1<="NODE-A";
end if;
end process c2;
c3 : process(en_nodeb,clr)
begin
if clr='1' then
n2<="0000";
r2<="XXXXXX";
elsif rising_edge(en_nodeb) then
n2<="1011"; --B
r2<="NODE-A";
end if;
end process c3;
c4 : process(en_nodec,clr)
begin
if clr='1' then
n3<="0000";
r3<="XXXXXX";
elsif rising_edge(en_nodec) then
n3<="1100"; -- c
r3<="NODE-C";
end if;
end process c4;
c5 : process(en_noded,clr)
begin
if clr='1' then
n4<="0000";
r4<="XXXXXX";
elsif rising_edge(en_noded) then
n4<="1010"; -- D
r4<="NODE-D";
end if;
end process c5;
c6 : process(en_nodee,clr)
begin
if clr='1' then
n5<="0000";
r5<="XXXXXX";
elsif rising_edge(en_nodee) then
n5<="1010"; -- E
r5<="NODE-E";
end if;
end process c6;
e1<=en_nodea;
e2<=en_nodeb;
e3<=en_nodec;
e4<=en_noded;
e5<=en_nodee;
end behave;
